forked from OSchip/llvm-project
Longs are in one register on PowerPC 64; use appropriate instructions to operate on them.
llvm-svn: 15711
This commit is contained in:
Nate Begeman
parent
765cb5f844
commit
2e8bfa2364
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@ -1867,38 +1867,14 @@ void ISel::doMultiply(MachineBasicBlock *MBB,
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// 64 x 64 -> 64
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if (Class0 == cLong && Class1 == cLong) {
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unsigned Tmp1 = makeAnotherReg(Type::IntTy);
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unsigned Tmp2 = makeAnotherReg(Type::IntTy);
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unsigned Tmp3 = makeAnotherReg(Type::IntTy);
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unsigned Tmp4 = makeAnotherReg(Type::IntTy);
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// FIXME: long is not split into two regs
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BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r+1);
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BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
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BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Op1r);
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BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r+1);
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BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
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BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
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return;
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}
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// 64 x 32 or less, promote 32 to 64 and do a 64 x 64
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if (Class0 == cLong && Class1 <= cInt) {
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unsigned Tmp0 = makeAnotherReg(Type::IntTy);
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unsigned Tmp1 = makeAnotherReg(Type::IntTy);
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unsigned Tmp2 = makeAnotherReg(Type::IntTy);
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unsigned Tmp3 = makeAnotherReg(Type::IntTy);
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unsigned Tmp4 = makeAnotherReg(Type::IntTy);
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if (Op1->getType()->isSigned())
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BuildMI(*MBB, IP, PPC::SRAWI, 2, Tmp0).addReg(Op1r).addImm(31);
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else
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BuildMI(*MBB, IP, PPC::LI, 2, Tmp0).addSImm(0);
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// FIXME: long is not split into two regs
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BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r);
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BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r);
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BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Tmp0);
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BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r);
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BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
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// FIXME: CLEAR or SIGN EXTEND Op1
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BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
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return;
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}
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@ -2139,103 +2115,27 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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//
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if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
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unsigned Amount = CUI->getValue();
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if (Amount < 32) {
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if (isLeftShift) {
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// FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
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// FIXME: long
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
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.addImm(Amount).addImm(0).addImm(31-Amount);
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BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
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.addImm(Amount).addImm(32-Amount).addImm(31);
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
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.addImm(Amount).addImm(0).addImm(31-Amount);
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assert(Amount < 64 && "Invalid immediate shift amount!");
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if (isLeftShift) {
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BuildMI(*MBB, IP, PPC::RLDICR, 3, DestReg).addReg(SrcReg).addImm(Amount)
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.addImm(63-Amount);
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} else {
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if (isSigned) {
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BuildMI(*MBB, IP, PPC::SRADI, 2, DestReg).addReg(SrcReg)
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.addImm(Amount);
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} else {
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// FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
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// FIXME: long
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
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.addImm(32-Amount).addImm(Amount).addImm(31);
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BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
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.addImm(32-Amount).addImm(0).addImm(Amount-1);
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
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.addImm(32-Amount).addImm(Amount).addImm(31);
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}
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} else { // Shifting more than 32 bits
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Amount -= 32;
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if (isLeftShift) {
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if (Amount != 0) {
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// FIXME: long
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg+1)
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.addImm(Amount).addImm(0).addImm(31-Amount);
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} else {
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// FIXME: long
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg+1)
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.addReg(SrcReg+1);
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}
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BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
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} else {
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if (Amount != 0) {
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if (isSigned)
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BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg+1).addReg(SrcReg)
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.addImm(Amount);
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else
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg)
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.addImm(32-Amount).addImm(Amount).addImm(31);
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} else {
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
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.addReg(SrcReg);
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}
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BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
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BuildMI(*MBB, IP, PPC::RLDICL, 3, DestReg).addReg(SrcReg)
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.addImm(64-Amount).addImm(Amount);
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}
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}
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} else {
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unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
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unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
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unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
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unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
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unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
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unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
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unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
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unsigned ShiftReg = getReg (ShiftAmount, MBB, IP);
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if (isLeftShift) {
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BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
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.addSImm(32);
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BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg2).addReg(SrcReg)
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.addReg(ShiftAmountReg);
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BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg3).addReg(SrcReg+1)
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.addReg(TmpReg1);
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BuildMI(*MBB, IP, PPC::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
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BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
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.addSImm(-32);
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BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg6).addReg(SrcReg+1)
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.addReg(TmpReg5);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(TmpReg4)
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.addReg(TmpReg6);
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BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
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.addReg(ShiftAmountReg);
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BuildMI(*MBB, IP, PPC::SLD, 2, DestReg).addReg(SrcReg).addReg(ShiftReg);
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} else {
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if (isSigned) {
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// FIXME: Unimplemented
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// Page C-3 of the PowerPC 32bit Programming Environments Manual
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std::cerr << "ERROR: Unimplemented: signed right shift of long\n";
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abort();
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} else {
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BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
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.addSImm(32);
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BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
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.addReg(ShiftAmountReg);
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BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
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.addReg(TmpReg1);
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BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
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.addReg(TmpReg3);
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BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
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.addSImm(-32);
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BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg6).addReg(SrcReg)
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.addReg(TmpReg5);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(TmpReg4)
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.addReg(TmpReg6);
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BuildMI(*MBB, IP, PPC::SRW, 2, DestReg).addReg(SrcReg)
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.addReg(ShiftAmountReg);
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}
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unsigned Opcode = (isSigned) ? PPC::SRAD : PPC::SRD;
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BuildMI(*MBB, IP, Opcode, DestReg).addReg(SrcReg).addReg(ShiftReg);
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}
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}
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return;
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@ -2688,16 +2588,7 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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if (sourceUnsigned && destUnsigned) {
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// handle long dest class now to keep switch clean
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if (DestClass == cLong) {
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// FIXME: long
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if (SrcClass == cLong) {
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1)
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.addReg(SrcReg+1);
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} else {
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BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
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.addReg(SrcReg);
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}
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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return;
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}
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@ -2730,16 +2621,7 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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if (!sourceUnsigned && !destUnsigned) {
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// handle long dest class now to keep switch clean
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if (DestClass == cLong) {
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// FIXME: long
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if (SrcClass == cLong) {
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1)
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.addReg(SrcReg+1);
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} else {
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BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
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.addReg(SrcReg);
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}
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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return;
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}
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@ -2778,16 +2660,7 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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if (sourceUnsigned && !destUnsigned) {
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// handle long dest class now to keep switch clean
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if (DestClass == cLong) {
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// FIXME: long
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if (SrcClass == cLong) {
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1).
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addReg(SrcReg+1);
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} else {
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BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
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.addReg(SrcReg);
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}
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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return;
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}
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@ -2830,16 +2703,7 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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if (!sourceUnsigned && destUnsigned) {
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// handle long dest class now to keep switch clean
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if (DestClass == cLong) {
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// FIXME: long
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if (SrcClass == cLong) {
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg+1)
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.addReg(SrcReg+1);
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} else {
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BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
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.addReg(SrcReg);
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}
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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return;
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}
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