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[MachineScheduler] Fix operand scheduling for pre/post-increment loads 

Differential revision: https://reviews.llvm.org/D87557
This commit is contained in:
Evgeny Leviant 2020-09-12 16:53:12 +03:00
parent 78de7297ab
commit 2e61cd1295
2 changed files with 9 additions and 9 deletions
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8
llvm/lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -3939,7 +3939,7 @@ class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
(outs GPR64sp:$wback, regtype:$Rt),
(ins GPR64sp:$Rn, simm9:$offset), asm,
"$Rn = $wback,@earlyclobber $wback", []>,
Sched<[WriteLD, WriteAdr]>;
Sched<[WriteAdr, WriteLD]>;
let mayStore = 1, mayLoad = 0 in
class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
@ -3985,7 +3985,7 @@ class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
(outs GPR64sp:$wback, regtype:$Rt),
(ins GPR64sp:$Rn, simm9:$offset),
asm, "$Rn = $wback,@earlyclobber $wback", []>,
Sched<[WriteLD, WriteAdr]>;
Sched<[WriteAdr, WriteLD]>;
let mayStore = 1, mayLoad = 0 in
class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
@ -4082,7 +4082,7 @@ class LoadPairPreIdx<bits<2> opc, bit V, RegisterOperand regtype,
: BaseLoadStorePairPreIdx<opc, V, 1,
(outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
(ins GPR64sp:$Rn, indextype:$offset), asm>,
Sched<[WriteLD, WriteLDHi, WriteAdr]>;
Sched<[WriteAdr, WriteLD, WriteLDHi]>;
let mayStore = 1, mayLoad = 0 in
class StorePairPreIdx<bits<2> opc, bit V, RegisterOperand regtype,
@ -4123,7 +4123,7 @@ class LoadPairPostIdx<bits<2> opc, bit V, RegisterOperand regtype,
: BaseLoadStorePairPostIdx<opc, V, 1,
(outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
(ins GPR64sp:$Rn, idxtype:$offset), asm>,
Sched<[WriteLD, WriteLDHi, WriteAdr]>;
Sched<[WriteAdr, WriteLD, WriteLDHi]>;
let mayStore = 1, mayLoad = 0 in
class StorePairPostIdx<bits<2> opc, bit V, RegisterOperand regtype,

10
llvm/test/tools/llvm-mca/AArch64/Exynos/load.s
View File

@ -20,7 +20,7 @@ ldpsw x0, x1, [sp, #8]!
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 1200
# ALL-NEXT: Total Cycles: 1904
# ALL-NEXT: Total Cycles: 1304
# M3-NEXT: Total uOps: 1600
# M4-NEXT: Total uOps: 1400
@ -28,11 +28,11 @@ ldpsw x0, x1, [sp, #8]!
# ALL: Dispatch Width: 6
# M3-NEXT: uOps Per Cycle: 0.84
# M4-NEXT: uOps Per Cycle: 0.74
# M5-NEXT: uOps Per Cycle: 0.74
# M3-NEXT: uOps Per Cycle: 1.23
# M4-NEXT: uOps Per Cycle: 1.07
# M5-NEXT: uOps Per Cycle: 1.07
# ALL-NEXT: IPC: 0.63
# ALL-NEXT: IPC: 0.92
# ALL-NEXT: Block RThroughput: 6.0
# ALL: Instruction Info: