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GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_round 

llvm-svn: 352298
This commit is contained in:
Matt Arsenault 2019-01-27 00:12:21 +00:00
parent ded2f82662
commit 2e5f900849
4 changed files with 97 additions and 10 deletions
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4
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -1417,7 +1417,9 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case TargetOpcode::G_FLOG:
case TargetOpcode::G_FLOG2:
case TargetOpcode::G_FLOG10:
case TargetOpcode::G_FCEIL: {
case TargetOpcode::G_FCEIL:
case TargetOpcode::G_INTRINSIC_ROUND:
case TargetOpcode::G_INTRINSIC_TRUNC: {
unsigned NarrowSize = NarrowTy.getSizeInBits();
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Flags = MI.getFlags();

3
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View File

@ -179,7 +179,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
.scalarize(0);
getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
.legalFor({S32, S64});
.legalFor({S32, S64})
.scalarize(0);
for (LLT PtrTy : AddrSpaces) {
LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());

50
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
View File

@ -2,24 +2,66 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_intrinsic_round_f32
name: test_intrinsic_round_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_intrinsic_round_f32
; CHECK-LABEL: name: test_intrinsic_round_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_ROUND %0
$vgpr0 = COPY %0
...
---
name: test_intrinsic_round_f64
name: test_intrinsic_round_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_intrinsic_round_f64
; CHECK-LABEL: name: test_intrinsic_round_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $vgpr0_vgpr1 = COPY [[INTRINSIC_ROUND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_intrinsic_round_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_intrinsic_round_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[UV]]
; CHECK: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[UV1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_ROUND]](s32), [[INTRINSIC_ROUND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_intrinsic_round_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_intrinsic_round_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[UV]]
; CHECK: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[UV1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INTRINSIC_ROUND]](s64), [[INTRINSIC_ROUND1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...

50
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
View File

@ -2,24 +2,66 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_intrinsic_trunc_f32
name: test_intrinsic_trunc_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_intrinsic_trunc_f32
; CHECK-LABEL: name: test_intrinsic_trunc_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
$vgpr0 = COPY %0
...
---
name: test_intrinsic_trunc_f64
name: test_intrinsic_trunc_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_intrinsic_trunc_f64
; CHECK-LABEL: name: test_intrinsic_trunc_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
; CHECK: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_intrinsic_trunc_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_intrinsic_trunc_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
; CHECK: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s32), [[INTRINSIC_TRUNC1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_intrinsic_trunc_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_intrinsic_trunc_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
; CHECK: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s64), [[INTRINSIC_TRUNC1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...