forked from OSchip/llvm-project
[ppc64] Enable sibling call optimization on ppc64 ELFv1/ELFv2 abi
This patch enable sibling call optimization on ppc64 ELFv1/ELFv2 abi, and add a couple of test cases. This patch also passed llvm/clang bootstrap test, and spec2006 build/run/result validation. Original issue: https://llvm.org/bugs/show_bug.cgi?id=25617 Great thanks to Tom's (tjablin) help, he contributed a lot to this patch. Thanks Hal and Kit's invaluable opinions! Reviewers: hfinkel kbarton http://reviews.llvm.org/D16315 llvm-svn: 265506
This commit is contained in:
Chuang-Yu Cheng
parent
024a623c55
commit
2e5973ef74
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@ -19,6 +19,7 @@
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#include "PPCTargetMachine.h"
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#include "PPCTargetObjectFile.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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@ -36,12 +37,15 @@
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-lowering"
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static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
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cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
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@ -51,6 +55,12 @@ cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hi
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static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
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cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
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static cl::opt<bool> DisableSCO("disable-ppc-sco",
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cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
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STATISTIC(NumTailCalls, "Number of tail calls");
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STATISTIC(NumSiblingCalls, "Number of sibling calls");
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// FIXME: Remove this once the bug has been fixed!
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extern cl::opt<bool> ANDIGlueBug;
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@ -3842,6 +3852,176 @@ static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
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return SPDiff;
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}
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static bool isFunctionGlobalAddress(SDValue Callee);
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static bool
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resideInSameModule(SDValue Callee, Reloc::Model RelMod) {
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// If !G, Callee can be an external symbol.
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GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
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if (!G) return false;
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const GlobalValue *GV = G->getGlobal();
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if (GV->isDeclaration()) return false;
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switch(GV->getLinkage()) {
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default: llvm_unreachable("unknow linkage type");
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case GlobalValue::AvailableExternallyLinkage:
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case GlobalValue::ExternalWeakLinkage:
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return false;
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// Callee with weak linkage is allowed if it has hidden or protected
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// visibility
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case GlobalValue::LinkOnceAnyLinkage:
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case GlobalValue::LinkOnceODRLinkage: // e.g. c++ inline functions
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case GlobalValue::WeakAnyLinkage:
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case GlobalValue::WeakODRLinkage: // e.g. c++ template instantiation
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if (GV->hasDefaultVisibility())
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return false;
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case GlobalValue::ExternalLinkage:
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case GlobalValue::InternalLinkage:
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case GlobalValue::PrivateLinkage:
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break;
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}
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// With '-fPIC', calling default visiblity function need insert 'nop' after
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// function call, no matter that function resides in same module or not, so
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// we treat it as in different module.
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if (RelMod == Reloc::PIC_ && GV->hasDefaultVisibility())
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return false;
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return true;
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}
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static bool
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needStackSlotPassParameters(const PPCSubtarget &Subtarget,
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const SmallVectorImpl<ISD::OutputArg> &Outs) {
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assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64());
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const unsigned PtrByteSize = 8;
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const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
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static const MCPhysReg GPR[] = {
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PPC::X3, PPC::X4, PPC::X5, PPC::X6,
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PPC::X7, PPC::X8, PPC::X9, PPC::X10,
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};
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static const MCPhysReg VR[] = {
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PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
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PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
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};
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const unsigned NumGPRs = array_lengthof(GPR);
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const unsigned NumFPRs = 13;
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const unsigned NumVRs = array_lengthof(VR);
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const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
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unsigned NumBytes = LinkageSize;
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unsigned AvailableFPRs = NumFPRs;
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unsigned AvailableVRs = NumVRs;
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for (const ISD::OutputArg& Param : Outs) {
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if (Param.Flags.isNest()) continue;
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if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
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PtrByteSize, LinkageSize, ParamAreaSize,
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NumBytes, AvailableFPRs, AvailableVRs,
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Subtarget.hasQPX()))
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return true;
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}
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return false;
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}
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static bool
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hasSameArgumentList(const Function *CallerFn, ImmutableCallSite *CS) {
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if (CS->arg_size() != CallerFn->getArgumentList().size())
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return false;
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ImmutableCallSite::arg_iterator CalleeArgIter = CS->arg_begin();
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ImmutableCallSite::arg_iterator CalleeArgEnd = CS->arg_end();
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Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
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for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
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const Value* CalleeArg = *CalleeArgIter;
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const Value* CallerArg = &(*CallerArgIter);
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if (CalleeArg == CallerArg)
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continue;
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// e.g. @caller([4 x i64] %a, [4 x i64] %b) {
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// tail call @callee([4 x i64] undef, [4 x i64] %b)
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// }
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// 1st argument of callee is undef and has the same type as caller.
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if (CalleeArg->getType() == CallerArg->getType() &&
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isa<UndefValue>(CalleeArg))
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continue;
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return false;
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}
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return true;
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}
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bool
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PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
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SDValue Callee,
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CallingConv::ID CalleeCC,
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ImmutableCallSite *CS,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const {
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bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
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if (DisableSCO && !TailCallOpt) return false;
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// Variadic argument functions are not supported.
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if (isVarArg) return false;
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MachineFunction &MF = DAG.getMachineFunction();
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CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
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// Tail or Sibling call optimization (TCO/SCO) needs callee and caller has
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// the same calling convention
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if (CallerCC != CalleeCC) return false;
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// SCO support C calling convention
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if (CalleeCC != CallingConv::Fast && CalleeCC != CallingConv::C)
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return false;
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// Functions containing by val parameters are not supported.
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if (std::any_of(Ins.begin(), Ins.end(),
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[](const ISD::InputArg& IA) { return IA.Flags.isByVal(); }))
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return false;
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// No TCO/SCO on indirect call because Caller have to restore its TOC
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if (!isFunctionGlobalAddress(Callee) &&
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!isa<ExternalSymbolSDNode>(Callee))
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return false;
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// Check if Callee resides in the same module, because for now, PPC64 SVR4 ABI
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// (ELFv1/ELFv2) doesn't allow tail calls to a symbol resides in another
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// module.
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// ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
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if (!resideInSameModule(Callee, getTargetMachine().getRelocationModel()))
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return false;
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// TCO allows altering callee ABI, so we don't have to check further.
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if (CalleeCC == CallingConv::Fast && TailCallOpt)
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return true;
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if (DisableSCO) return false;
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// If callee use the same argument list that caller is using, then we can
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// apply SCO on this case. If it is not, then we need to check if callee needs
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// stack for passing arguments.
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if (!hasSameArgumentList(MF.getFunction(), CS) &&
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needStackSlotPassParameters(Subtarget, Outs)) {
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return false;
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}
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return true;
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}
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Targets which want to do tail call
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/// optimization should implement this function.
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@ -4479,9 +4659,32 @@ PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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bool IsPatchPoint = CLI.IsPatchPoint;
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ImmutableCallSite *CS = CLI.CS;
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if (isTailCall)
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
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Ins, DAG);
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if (isTailCall) {
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if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
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isTailCall =
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IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
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isVarArg, Outs, Ins, DAG);
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else
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
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Ins, DAG);
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if (isTailCall) {
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++NumTailCalls;
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if (!getTargetMachine().Options.GuaranteedTailCallOpt)
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++NumSiblingCalls;
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assert(isa<GlobalAddressSDNode>(Callee) &&
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"Callee should be an llvm::Function object.");
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DEBUG(
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const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
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const unsigned Width = 80 - strlen("TCO caller: ")
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- strlen(", callee linkage: 0, 0");
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dbgs() << "TCO caller: "
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<< left_justify(DAG.getMachineFunction().getName(), Width)
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<< ", callee linkage: "
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<< GV->getVisibility() << ", " << GV->getLinkage() << "\n"
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);
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}
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}
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if (!isTailCall && CS && CS->isMustTailCall())
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report_fatal_error("failed to perform tail call elimination on a call "
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@ -4760,12 +4963,16 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
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bool isLittleEndian = Subtarget.isLittleEndian();
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unsigned NumOps = Outs.size();
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bool hasNest = false;
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bool IsSibCall = false;
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
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unsigned PtrByteSize = 8;
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MachineFunction &MF = DAG.getMachineFunction();
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if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
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IsSibCall = true;
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// Mark this function as potentially containing a function that contains a
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// tail call. As a consequence the frame pointer will be used for dynamicalloc
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// and restoring the callers stack pointer in this functions epilog. This is
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@ -4885,9 +5092,12 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
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CallConv == CallingConv::Fast)
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NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
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int SPDiff = 0;
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// Calculate by how many bytes the stack has to be adjusted in case of tail
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// call optimization.
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int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
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if (!IsSibCall)
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SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
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// To protect arguments on the stack from being clobbered in a tail call,
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// force all the loads to happen before doing any other lowering.
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@ -4896,8 +5106,9 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
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dl);
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if (!IsSibCall)
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getIntPtrConstant(NumBytes, dl, true), dl);
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SDValue CallSeqStart = Chain;
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// Load the return address and frame pointer so it can be move somewhere else
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@ -5366,7 +5577,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
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InFlag = Chain.getValue(1);
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}
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if (isTailCall)
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if (isTailCall && !IsSibCall)
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PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
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FPOp, true, TailCallArguments);
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@ -713,6 +713,16 @@ namespace llvm {
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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bool
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IsEligibleForTailCallOptimization_64SVR4(
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SDValue Callee,
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CallingConv::ID CalleeCC,
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ImmutableCallSite *CS,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
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int SPDiff,
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SDValue Chain,
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@ -14,7 +14,8 @@ define weak void @foo_weak() nounwind {
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define void @test_direct() nounwind readnone {
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; CHECK-LABEL: test_direct:
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tail call void @foo() nounwind
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; CHECK: bl foo
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; Because of tail call optimization, it can be 'b' instruction.
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; CHECK: [[BR:b[l]?]] foo
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; CHECK-NOT: nop
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ret void
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}
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@ -0,0 +1,46 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SHRK
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SHRK
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%"class.clang::NamedDecl" = type { i32 }
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declare void @__assert_fail();
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define i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv(
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%"class.clang::NamedDecl"* %this) {
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entry:
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%tobool = icmp eq %"class.clang::NamedDecl"* %this, null
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br i1 %tobool, label %cond.false, label %exit
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cond.false:
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tail call void @__assert_fail()
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unreachable
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exit:
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%DeclKind = getelementptr inbounds
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%"class.clang::NamedDecl",
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%"class.clang::NamedDecl"* %this, i64 0, i32 0
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%bf.load = load i32, i32* %DeclKind, align 4
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%call.i = tail call i8 @LVComputationKind(
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%"class.clang::NamedDecl"* %this,
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i32 %bf.load)
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ret i8 %call.i
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; CHECK-SCO-SHRK-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
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; CHECK-SCO-SHRK: b LVComputationKind
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; CHECK-SCO-SHRK: #TC_RETURNd8
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; CHECK-SCO-SHRK: stdu 1, -{{[0-9]+}}(1)
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; CHECK-SCO-SHRK: bl __assert_fail
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;
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; CHECK-SCO-ONLY-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
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; CHECK-SCO-ONLY: stdu 1, -{{[0-9]+}}(1)
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; CHECK-SCO-ONLY: b LVComputationKind
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; CHECK-SCO-ONLY: #TC_RETURNd8
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; CHECK-SCO-ONLY: bl __assert_fail
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}
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define fastcc i8 @LVComputationKind(
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%"class.clang::NamedDecl"* %D,
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i32 %computation) {
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ret i8 0
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}
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@ -0,0 +1,191 @@
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; RUN: llc < %s -O1 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO
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; RUN: llc < %s -O1 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX
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; RUN: llc < %s -O1 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX
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; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because
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; only Power8 (and later) fully support LE.
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%S_56 = type { [13 x i32], i32 }
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%S_64 = type { [15 x i32], i32 }
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%S_32 = type { [7 x i32], i32 }
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; Function Attrs: noinline nounwind
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define void @callee_56_copy([7 x i64] %a, %S_56* %b) #0 { ret void }
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define void @callee_64_copy([8 x i64] %a, %S_64* %b) #0 { ret void }
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; Function Attrs: nounwind
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define void @caller_56_reorder_copy(%S_56* %b, [7 x i64] %a) #1 {
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tail call void @callee_56_copy([7 x i64] %a, %S_56* %b)
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ret void
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; CHECK-SCO-LABEL: caller_56_reorder_copy:
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; CHECK-SCO-NOT: stdu 1
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; CHECK-SCO: TC_RETURNd8 callee_56_copy
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}
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|
||||
define void @caller_64_reorder_copy(%S_64* %b, [8 x i64] %a) #1 {
|
||||
tail call void @callee_64_copy([8 x i64] %a, %S_64* %b)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: caller_64_reorder_copy:
|
||||
; CHECK-SCO: bl callee_64_copy
|
||||
}
|
||||
|
||||
define void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b) #0 { ret void }
|
||||
define void @caller_64_64_copy([8 x i64] %a, [8 x i64] %b) #1 {
|
||||
tail call void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: caller_64_64_copy:
|
||||
; CHECK-SCO: b callee_64_64_copy
|
||||
}
|
||||
|
||||
define void @caller_64_64_reorder_copy([8 x i64] %a, [8 x i64] %b) #1 {
|
||||
tail call void @callee_64_64_copy([8 x i64] %b, [8 x i64] %a)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: caller_64_64_reorder_copy:
|
||||
; CHECK-SCO: bl callee_64_64_copy
|
||||
}
|
||||
|
||||
define void @caller_64_64_undef_copy([8 x i64] %a, [8 x i64] %b) #1 {
|
||||
tail call void @callee_64_64_copy([8 x i64] %a, [8 x i64] undef)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: caller_64_64_undef_copy:
|
||||
; CHECK-SCO: b callee_64_64_copy
|
||||
}
|
||||
|
||||
define void @arg8_callee(
|
||||
float %a, i32 signext %b, float %c, i32* %d,
|
||||
i8 zeroext %e, float %f, i32* %g, i32 signext %h)
|
||||
{
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @arg8_caller(float %a, i32 signext %b, i8 zeroext %c, i32* %d) {
|
||||
entry:
|
||||
tail call void @arg8_callee(float undef, i32 signext undef, float undef,
|
||||
i32* %d, i8 zeroext undef, float undef,
|
||||
i32* undef, i32 signext undef)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: arg8_caller:
|
||||
; CHECK-SCO: b arg8_callee
|
||||
}
|
||||
|
||||
; Struct return test
|
||||
|
||||
; Function Attrs: noinline nounwind
|
||||
define void @callee_sret_56(%S_56* noalias sret %agg.result) #0 { ret void }
|
||||
define void @callee_sret_32(%S_32* noalias sret %agg.result) #0 { ret void }
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @caller_do_something_sret_32(%S_32* noalias sret %agg.result) #1 {
|
||||
%1 = alloca %S_56, align 4
|
||||
%2 = bitcast %S_56* %1 to i8*
|
||||
call void @callee_sret_56(%S_56* nonnull sret %1)
|
||||
tail call void @callee_sret_32(%S_32* sret %agg.result)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: caller_do_something_sret_32:
|
||||
; CHECK-SCO: stdu 1
|
||||
; CHECK-SCO: bl callee_sret_56
|
||||
; CHECK-SCO: addi 1
|
||||
; CHECK-SCO: TC_RETURNd8 callee_sret_32
|
||||
}
|
||||
|
||||
define void @caller_local_sret_32(%S_32* %a) #1 {
|
||||
%tmp = alloca %S_32, align 4
|
||||
tail call void @callee_sret_32(%S_32* nonnull sret %tmp)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: caller_local_sret_32:
|
||||
; CHECK-SCO: bl callee_sret_32
|
||||
}
|
||||
|
||||
attributes #0 = { noinline nounwind }
|
||||
attributes #1 = { nounwind }
|
||||
|
||||
; vector <4 x i1> test
|
||||
|
||||
define void @callee_v4i1(i8 %a, <4 x i1> %b, <4 x i1> %c) { ret void }
|
||||
define void @caller_v4i1_reorder(i8 %a, <4 x i1> %b, <4 x i1> %c) {
|
||||
tail call void @callee_v4i1(i8 %a, <4 x i1> %c, <4 x i1> %b)
|
||||
ret void
|
||||
|
||||
; <4 x i1> is 32 bytes aligned, if subtarget doesn't support qpx, then we can't
|
||||
; place b, c to qpx register, so we can't do sco on caller_v4i1_reorder
|
||||
|
||||
; CHECK-SCO-LABEL: caller_v4i1_reorder:
|
||||
; CHECK-SCO: bl callee_v4i1
|
||||
|
||||
; CHECK-SCO-HASQPX-LABEL: caller_v4i1_reorder:
|
||||
; CHECK-SCO-HASQPX: b callee_v4i1
|
||||
}
|
||||
|
||||
define void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) { ret void }
|
||||
define void @f128_caller(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) {
|
||||
tail call void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: f128_caller:
|
||||
; CHECK-SCO: b f128_callee
|
||||
}
|
||||
|
||||
; weak linkage test
|
||||
%class.T = type { [2 x i8] }
|
||||
|
||||
define weak_odr hidden void @wo_hcallee(%class.T* %this, i8* %c) { ret void }
|
||||
define void @wo_hcaller(%class.T* %this, i8* %c) {
|
||||
tail call void @wo_hcallee(%class.T* %this, i8* %c)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: wo_hcaller:
|
||||
; CHECK-SCO: b wo_hcallee
|
||||
}
|
||||
|
||||
define weak_odr protected void @wo_pcallee(%class.T* %this, i8* %c) { ret void }
|
||||
define void @wo_pcaller(%class.T* %this, i8* %c) {
|
||||
tail call void @wo_pcallee(%class.T* %this, i8* %c)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: wo_pcaller:
|
||||
; CHECK-SCO: b wo_pcallee
|
||||
}
|
||||
|
||||
define weak_odr void @wo_callee(%class.T* %this, i8* %c) { ret void }
|
||||
define void @wo_caller(%class.T* %this, i8* %c) {
|
||||
tail call void @wo_callee(%class.T* %this, i8* %c)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: wo_caller:
|
||||
; CHECK-SCO: bl wo_callee
|
||||
}
|
||||
|
||||
define weak protected void @w_pcallee(i8* %ptr) { ret void }
|
||||
define void @w_pcaller(i8* %ptr) {
|
||||
tail call void @w_pcallee(i8* %ptr)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: w_pcaller:
|
||||
; CHECK-SCO: b w_pcallee
|
||||
}
|
||||
|
||||
define weak hidden void @w_hcallee(i8* %ptr) { ret void }
|
||||
define void @w_hcaller(i8* %ptr) {
|
||||
tail call void @w_hcallee(i8* %ptr)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: w_hcaller:
|
||||
; CHECK-SCO: b w_hcallee
|
||||
}
|
||||
|
||||
define weak void @w_callee(i8* %ptr) { ret void }
|
||||
define void @w_caller(i8* %ptr) {
|
||||
tail call void @w_callee(i8* %ptr)
|
||||
ret void
|
||||
|
||||
; CHECK-SCO-LABEL: w_caller:
|
||||
; CHECK-SCO: bl w_callee
|
||||
}
|
||||
Loading…
Reference in New Issue