forked from OSchip/llvm-project
[CUDA] Implement __ldg using intrinsics.
Summary: Previously it was implemented as inline asm in the CUDA headers. This change allows us to use the [addr+imm] addressing mode when executing ld.global.nc instructions. This translates into a 1.3x speedup on some benchmarks that call this instruction from within an unrolled loop. Reviewers: tra, rsmith Subscribers: jhen, cfe-commits, jholewinski Differential Revision: http://reviews.llvm.org/D19990 llvm-svn: 270150
This commit is contained in:
Justin Lebar
parent
b926bdac4c
commit
2e4ecfdebe
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@ -566,4 +566,40 @@ BUILTIN(__nvvm_atom_cas_gen_ll, "LLiLLiD*LLiLLi", "n")
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BUILTIN(__nvvm_compiler_error, "vcC*4", "n")
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BUILTIN(__nvvm_compiler_warn, "vcC*4", "n")
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// __ldg. This is not implemented as a builtin by nvcc.
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BUILTIN(__nvvm_ldg_c, "ccC*", "")
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BUILTIN(__nvvm_ldg_s, "ssC*", "")
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BUILTIN(__nvvm_ldg_i, "iiC*", "")
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BUILTIN(__nvvm_ldg_l, "LiLiC*", "")
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BUILTIN(__nvvm_ldg_ll, "LLiLLiC*", "")
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BUILTIN(__nvvm_ldg_uc, "UcUcC*", "")
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BUILTIN(__nvvm_ldg_us, "UsUsC*", "")
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BUILTIN(__nvvm_ldg_ui, "UiUiC*", "")
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BUILTIN(__nvvm_ldg_ul, "ULiULiC*", "")
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BUILTIN(__nvvm_ldg_ull, "ULLiULLiC*", "")
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BUILTIN(__nvvm_ldg_f, "ffC*", "")
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BUILTIN(__nvvm_ldg_d, "ddC*", "")
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BUILTIN(__nvvm_ldg_c2, "E2cE2cC*", "")
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BUILTIN(__nvvm_ldg_c4, "E4cE4cC*", "")
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BUILTIN(__nvvm_ldg_s2, "E2sE2sC*", "")
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BUILTIN(__nvvm_ldg_s4, "E4sE4sC*", "")
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BUILTIN(__nvvm_ldg_i2, "E2iE2iC*", "")
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BUILTIN(__nvvm_ldg_i4, "E4iE4iC*", "")
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BUILTIN(__nvvm_ldg_ll2, "E2LLiE2LLiC*", "")
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BUILTIN(__nvvm_ldg_uc2, "E2UcE2UcC*", "")
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BUILTIN(__nvvm_ldg_uc4, "E4UcE4UcC*", "")
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BUILTIN(__nvvm_ldg_us2, "E2UsE2UsC*", "")
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BUILTIN(__nvvm_ldg_us4, "E4UsE4UsC*", "")
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BUILTIN(__nvvm_ldg_ui2, "E2UiE2UiC*", "")
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BUILTIN(__nvvm_ldg_ui4, "E4UiE4UiC*", "")
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BUILTIN(__nvvm_ldg_ull2, "E2ULLiE2ULLiC*", "")
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BUILTIN(__nvvm_ldg_f2, "E2fE2fC*", "")
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BUILTIN(__nvvm_ldg_f4, "E4fE4fC*", "")
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BUILTIN(__nvvm_ldg_d2, "E2dE2dC*", "")
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#undef BUILTIN
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@ -7349,6 +7349,17 @@ Value *CodeGenFunction::EmitSystemZBuiltinExpr(unsigned BuiltinID,
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Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
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const CallExpr *E) {
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auto MakeLdg = [&](unsigned IntrinsicID) {
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Value *Ptr = EmitScalarExpr(E->getArg(0));
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AlignmentSource AlignSource;
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clang::CharUnits Align =
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getNaturalPointeeTypeAlignment(E->getArg(0)->getType(), &AlignSource);
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return Builder.CreateCall(
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CGM.getIntrinsic(IntrinsicID, {Ptr->getType()->getPointerElementType(),
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Ptr->getType()}),
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{Ptr, ConstantInt::get(Builder.getInt32Ty(), Align.getQuantity())});
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};
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switch (BuiltinID) {
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case NVPTX::BI__nvvm_atom_add_gen_i:
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case NVPTX::BI__nvvm_atom_add_gen_l:
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@ -7433,6 +7444,40 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
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return Builder.CreateCall(FnALD32, {Ptr, Val});
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}
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case NVPTX::BI__nvvm_ldg_c:
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case NVPTX::BI__nvvm_ldg_c2:
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case NVPTX::BI__nvvm_ldg_c4:
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case NVPTX::BI__nvvm_ldg_s:
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case NVPTX::BI__nvvm_ldg_s2:
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case NVPTX::BI__nvvm_ldg_s4:
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case NVPTX::BI__nvvm_ldg_i:
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case NVPTX::BI__nvvm_ldg_i2:
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case NVPTX::BI__nvvm_ldg_i4:
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case NVPTX::BI__nvvm_ldg_l:
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case NVPTX::BI__nvvm_ldg_ll:
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case NVPTX::BI__nvvm_ldg_ll2:
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case NVPTX::BI__nvvm_ldg_uc:
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case NVPTX::BI__nvvm_ldg_uc2:
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case NVPTX::BI__nvvm_ldg_uc4:
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case NVPTX::BI__nvvm_ldg_us:
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case NVPTX::BI__nvvm_ldg_us2:
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case NVPTX::BI__nvvm_ldg_us4:
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case NVPTX::BI__nvvm_ldg_ui:
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case NVPTX::BI__nvvm_ldg_ui2:
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case NVPTX::BI__nvvm_ldg_ui4:
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case NVPTX::BI__nvvm_ldg_ul:
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case NVPTX::BI__nvvm_ldg_ull:
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case NVPTX::BI__nvvm_ldg_ull2:
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// PTX Interoperability section 2.2: "For a vector with an even number of
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// elements, its alignment is set to number of elements times the alignment
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// of its member: n*alignof(t)."
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return MakeLdg(Intrinsic::nvvm_ldg_global_i);
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case NVPTX::BI__nvvm_ldg_f:
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case NVPTX::BI__nvvm_ldg_f2:
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case NVPTX::BI__nvvm_ldg_f4:
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case NVPTX::BI__nvvm_ldg_d:
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case NVPTX::BI__nvvm_ldg_d2:
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return MakeLdg(Intrinsic::nvvm_ldg_global_f);
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default:
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return nullptr;
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}
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@ -21,6 +21,7 @@ set(files
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bmi2intrin.h
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bmiintrin.h
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__clang_cuda_cmath.h
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__clang_cuda_intrinsics.h
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__clang_cuda_math_forward_declares.h
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__clang_cuda_runtime_wrapper.h
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cpuid.h
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@ -0,0 +1,256 @@
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/*===--- __clang_cuda_intrinsics.h - Device-side CUDA intrinsic wrappers ---===
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __CLANG_CUDA_INTRINSICS_H__
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#define __CLANG_CUDA_INTRINSICS_H__
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#ifndef __CUDA__
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#error "This file is for CUDA compilation only."
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#endif
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// sm_32 intrinsics: __ldg and __funnelshift_{l,lc,r,rc}.
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// Prevent the vanilla sm_32 intrinsics header from being included.
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#define __SM_32_INTRINSICS_H__
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#define __SM_32_INTRINSICS_HPP__
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#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 320
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inline __device__ char __ldg(const char *ptr) { return __nvvm_ldg_c(ptr); }
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inline __device__ short __ldg(const short *ptr) { return __nvvm_ldg_s(ptr); }
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inline __device__ int __ldg(const int *ptr) { return __nvvm_ldg_i(ptr); }
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inline __device__ long __ldg(const long *ptr) { return __nvvm_ldg_l(ptr); }
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inline __device__ long long __ldg(const long long *ptr) {
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return __nvvm_ldg_ll(ptr);
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}
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inline __device__ unsigned char __ldg(const unsigned char *ptr) {
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return __nvvm_ldg_uc(ptr);
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}
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inline __device__ unsigned short __ldg(const unsigned short *ptr) {
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return __nvvm_ldg_us(ptr);
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}
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inline __device__ unsigned int __ldg(const unsigned int *ptr) {
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return __nvvm_ldg_ui(ptr);
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}
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inline __device__ unsigned long __ldg(const unsigned long *ptr) {
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return __nvvm_ldg_ul(ptr);
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}
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inline __device__ unsigned long long __ldg(const unsigned long long *ptr) {
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return __nvvm_ldg_ull(ptr);
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}
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inline __device__ float __ldg(const float *ptr) { return __nvvm_ldg_f(ptr); }
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inline __device__ double __ldg(const double *ptr) { return __nvvm_ldg_d(ptr); }
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inline __device__ char2 __ldg(const char2 *ptr) {
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typedef char c2 __attribute__((ext_vector_type(2)));
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// We can assume that ptr is aligned at least to char2's alignment, but the
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// load will assume that ptr is aligned to char2's alignment. This is only
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// safe if alignof(c2) <= alignof(char2).
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c2 rv = __nvvm_ldg_c2(reinterpret_cast<const c2 *>(ptr));
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char2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ char4 __ldg(const char4 *ptr) {
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typedef char c4 __attribute__((ext_vector_type(4)));
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c4 rv = __nvvm_ldg_c4(reinterpret_cast<const c4 *>(ptr));
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char4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ short2 __ldg(const short2 *ptr) {
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typedef short s2 __attribute__((ext_vector_type(2)));
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s2 rv = __nvvm_ldg_s2(reinterpret_cast<const s2 *>(ptr));
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short2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ short4 __ldg(const short4 *ptr) {
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typedef short s4 __attribute__((ext_vector_type(4)));
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s4 rv = __nvvm_ldg_s4(reinterpret_cast<const s4 *>(ptr));
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short4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ int2 __ldg(const int2 *ptr) {
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typedef int i2 __attribute__((ext_vector_type(2)));
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i2 rv = __nvvm_ldg_i2(reinterpret_cast<const i2 *>(ptr));
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int2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ int4 __ldg(const int4 *ptr) {
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typedef int i4 __attribute__((ext_vector_type(4)));
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i4 rv = __nvvm_ldg_i4(reinterpret_cast<const i4 *>(ptr));
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int4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ longlong2 __ldg(const longlong2 *ptr) {
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typedef long long ll2 __attribute__((ext_vector_type(2)));
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ll2 rv = __nvvm_ldg_ll2(reinterpret_cast<const ll2 *>(ptr));
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longlong2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ uchar2 __ldg(const uchar2 *ptr) {
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typedef unsigned char uc2 __attribute__((ext_vector_type(2)));
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uc2 rv = __nvvm_ldg_uc2(reinterpret_cast<const uc2 *>(ptr));
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uchar2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ uchar4 __ldg(const uchar4 *ptr) {
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typedef unsigned char uc4 __attribute__((ext_vector_type(4)));
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uc4 rv = __nvvm_ldg_uc4(reinterpret_cast<const uc4 *>(ptr));
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uchar4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ ushort2 __ldg(const ushort2 *ptr) {
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typedef unsigned short us2 __attribute__((ext_vector_type(2)));
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us2 rv = __nvvm_ldg_us2(reinterpret_cast<const us2 *>(ptr));
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ushort2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ ushort4 __ldg(const ushort4 *ptr) {
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typedef unsigned short us4 __attribute__((ext_vector_type(4)));
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us4 rv = __nvvm_ldg_us4(reinterpret_cast<const us4 *>(ptr));
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ushort4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ uint2 __ldg(const uint2 *ptr) {
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typedef unsigned int ui2 __attribute__((ext_vector_type(2)));
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ui2 rv = __nvvm_ldg_ui2(reinterpret_cast<const ui2 *>(ptr));
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uint2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ uint4 __ldg(const uint4 *ptr) {
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typedef unsigned int ui4 __attribute__((ext_vector_type(4)));
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ui4 rv = __nvvm_ldg_ui4(reinterpret_cast<const ui4 *>(ptr));
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uint4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ ulonglong2 __ldg(const ulonglong2 *ptr) {
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typedef unsigned long long ull2 __attribute__((ext_vector_type(2)));
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ull2 rv = __nvvm_ldg_ull2(reinterpret_cast<const ull2 *>(ptr));
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ulonglong2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ float2 __ldg(const float2 *ptr) {
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typedef float f2 __attribute__((ext_vector_type(2)));
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f2 rv = __nvvm_ldg_f2(reinterpret_cast<const f2 *>(ptr));
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float2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ float4 __ldg(const float4 *ptr) {
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typedef float f4 __attribute__((ext_vector_type(4)));
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f4 rv = __nvvm_ldg_f4(reinterpret_cast<const f4 *>(ptr));
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float4 ret;
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ret.w = rv[0];
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ret.x = rv[1];
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ret.y = rv[2];
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ret.z = rv[3];
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return ret;
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}
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inline __device__ double2 __ldg(const double2 *ptr) {
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typedef double d2 __attribute__((ext_vector_type(2)));
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d2 rv = __nvvm_ldg_d2(reinterpret_cast<const d2 *>(ptr));
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double2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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// TODO: Implement these as intrinsics, so the backend can work its magic on
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// these. Alternatively, we could implement these as plain C and try to get
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// llvm to recognize the relevant patterns.
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inline __device__ unsigned __funnelshift_l(unsigned low32, unsigned high32,
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unsigned shiftWidth) {
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unsigned result;
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asm("shf.l.wrap.b32 %0, %1, %2, %3;"
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: "=r"(result)
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: "r"(low32), "r"(high32), "r"(shiftWidth));
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return result;
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}
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inline __device__ unsigned __funnelshift_lc(unsigned low32, unsigned high32,
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unsigned shiftWidth) {
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unsigned result;
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asm("shf.l.clamp.b32 %0, %1, %2, %3;"
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: "=r"(result)
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: "r"(low32), "r"(high32), "r"(shiftWidth));
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return result;
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}
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inline __device__ unsigned __funnelshift_r(unsigned low32, unsigned high32,
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unsigned shiftWidth) {
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unsigned result;
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asm("shf.r.wrap.b32 %0, %1, %2, %3;"
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: "=r"(result)
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: "r"(low32), "r"(high32), "r"(shiftWidth));
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return result;
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}
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inline __device__ unsigned __funnelshift_rc(unsigned low32, unsigned high32,
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unsigned shiftWidth) {
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unsigned ret;
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asm("shf.r.clamp.b32 %0, %1, %2, %3;"
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: "=r"(ret)
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: "r"(low32), "r"(high32), "r"(shiftWidth));
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return ret;
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}
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#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 320
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#endif // defined(__CLANG_CUDA_INTRINSICS_H__)
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@ -188,7 +188,10 @@ static inline __device__ void __brkpt(int __c) { __brkpt(); }
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// sm_30_intrinsics.h has declarations that use default argument, so
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// we have to include it and it will in turn include .hpp
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#include "sm_30_intrinsics.h"
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#include "sm_32_intrinsics.hpp"
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// Don't include sm_32_intrinsics.h. That header defines __ldg using inline
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// asm, but we want to define it using builtins, because we can't use the
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// [addr+imm] addressing mode if we use the inline asm in the header.
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#undef __MATH_FUNCTIONS_HPP__
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||||
|
||||
|
|
@ -278,6 +281,7 @@ __device__ inline __cuda_builtin_gridDim_t::operator dim3() const {
|
|||
}
|
||||
|
||||
#include <__clang_cuda_cmath.h>
|
||||
#include <__clang_cuda_intrinsics.h>
|
||||
|
||||
// curand_mtgp32_kernel helpfully redeclares blockDim and threadIdx in host
|
||||
// mode, giving them their "proper" types of dim3 and uint3. This is
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
// REQUIRES: nvptx-registered-target
|
||||
// RUN: %clang_cc1 -triple nvptx-unknown-unknown -fcuda-is-device -S -emit-llvm -o - -x cuda %s | FileCheck %s
|
||||
// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -fcuda-is-device -S -emit-llvm -o - -x cuda %s | FileCheck %s
|
||||
// RUN: %clang_cc1 -triple nvptx-unknown-unknown -fcuda-is-device -S -emit-llvm -o - -x cuda %s | \
|
||||
// RUN: FileCheck -check-prefix=CHECK -check-prefix=LP32 %s
|
||||
// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -fcuda-is-device -S -emit-llvm -o - -x cuda %s | \
|
||||
// RUN: FileCheck -check-prefix=CHECK -check-prefix=LP64 %s
|
||||
|
||||
#define __device__ __attribute__((device))
|
||||
#define __global__ __attribute__((global))
|
||||
|
|
@ -280,3 +282,103 @@ __device__ void nvvm_atom(float *fp, float f, int *ip, int i, unsigned int *uip,
|
|||
|
||||
// CHECK: ret
|
||||
}
|
||||
|
||||
// CHECK-LABEL: nvvm_ldg
|
||||
__device__ void nvvm_ldg(const void *p) {
|
||||
// CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0i8(i8* {{%[0-9]+}}, i32 1)
|
||||
// CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0i8(i8* {{%[0-9]+}}, i32 1)
|
||||
__nvvm_ldg_c((const char *)p);
|
||||
__nvvm_ldg_uc((const unsigned char *)p);
|
||||
|
||||
// CHECK: call i16 @llvm.nvvm.ldg.global.i.i16.p0i16(i16* {{%[0-9]+}}, i32 2)
|
||||
// CHECK: call i16 @llvm.nvvm.ldg.global.i.i16.p0i16(i16* {{%[0-9]+}}, i32 2)
|
||||
__nvvm_ldg_s((const short *)p);
|
||||
__nvvm_ldg_us((const unsigned short *)p);
|
||||
|
||||
// CHECK: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
||||
// CHECK: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
||||
__nvvm_ldg_i((const int *)p);
|
||||
__nvvm_ldg_ui((const unsigned int *)p);
|
||||
|
||||
// LP32: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
||||
// LP32: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
||||
// LP64: call i64 @llvm.nvvm.ldg.global.i.i64.p0i64(i64* {{%[0-9]+}}, i32 8)
|
||||
// LP64: call i64 @llvm.nvvm.ldg.global.i.i64.p0i64(i64* {{%[0-9]+}}, i32 8)
|
||||
__nvvm_ldg_l((const long *)p);
|
||||
__nvvm_ldg_ul((const unsigned long *)p);
|
||||
|
||||
// CHECK: call float @llvm.nvvm.ldg.global.f.f32.p0f32(float* {{%[0-9]+}}, i32 4)
|
||||
__nvvm_ldg_f((const float *)p);
|
||||
// CHECK: call double @llvm.nvvm.ldg.global.f.f64.p0f64(double* {{%[0-9]+}}, i32 8)
|
||||
__nvvm_ldg_d((const double *)p);
|
||||
|
||||
// In practice, the pointers we pass to __ldg will be aligned as appropriate
|
||||
// for the CUDA <type>N vector types (e.g. short4), which are not the same as
|
||||
// the LLVM vector types. However, each LLVM vector type has an alignment
|
||||
// less than or equal to its corresponding CUDA type, so we're OK.
|
||||
//
|
||||
// PTX Interoperability section 2.2: "For a vector with an even number of
|
||||
// elements, its alignment is set to number of elements times the alignment of
|
||||
// its member: n*alignof(t)."
|
||||
|
||||
// CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0v2i8(<2 x i8>* {{%[0-9]+}}, i32 2)
|
||||
// CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0v2i8(<2 x i8>* {{%[0-9]+}}, i32 2)
|
||||
typedef char char2 __attribute__((ext_vector_type(2)));
|
||||
typedef unsigned char uchar2 __attribute__((ext_vector_type(2)));
|
||||
__nvvm_ldg_c2((const char2 *)p);
|
||||
__nvvm_ldg_uc2((const uchar2 *)p);
|
||||
|
||||
// CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0v4i8(<4 x i8>* {{%[0-9]+}}, i32 4)
|
||||
// CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0v4i8(<4 x i8>* {{%[0-9]+}}, i32 4)
|
||||
typedef char char4 __attribute__((ext_vector_type(4)));
|
||||
typedef unsigned char uchar4 __attribute__((ext_vector_type(4)));
|
||||
__nvvm_ldg_c4((const char4 *)p);
|
||||
__nvvm_ldg_uc4((const uchar4 *)p);
|
||||
|
||||
// CHECK: call <2 x i16> @llvm.nvvm.ldg.global.i.v2i16.p0v2i16(<2 x i16>* {{%[0-9]+}}, i32 4)
|
||||
// CHECK: call <2 x i16> @llvm.nvvm.ldg.global.i.v2i16.p0v2i16(<2 x i16>* {{%[0-9]+}}, i32 4)
|
||||
typedef short short2 __attribute__((ext_vector_type(2)));
|
||||
typedef unsigned short ushort2 __attribute__((ext_vector_type(2)));
|
||||
__nvvm_ldg_s2((const short2 *)p);
|
||||
__nvvm_ldg_us2((const ushort2 *)p);
|
||||
|
||||
// CHECK: call <4 x i16> @llvm.nvvm.ldg.global.i.v4i16.p0v4i16(<4 x i16>* {{%[0-9]+}}, i32 8)
|
||||
// CHECK: call <4 x i16> @llvm.nvvm.ldg.global.i.v4i16.p0v4i16(<4 x i16>* {{%[0-9]+}}, i32 8)
|
||||
typedef short short4 __attribute__((ext_vector_type(4)));
|
||||
typedef unsigned short ushort4 __attribute__((ext_vector_type(4)));
|
||||
__nvvm_ldg_s4((const short4 *)p);
|
||||
__nvvm_ldg_us4((const ushort4 *)p);
|
||||
|
||||
// CHECK: call <2 x i32> @llvm.nvvm.ldg.global.i.v2i32.p0v2i32(<2 x i32>* {{%[0-9]+}}, i32 8)
|
||||
// CHECK: call <2 x i32> @llvm.nvvm.ldg.global.i.v2i32.p0v2i32(<2 x i32>* {{%[0-9]+}}, i32 8)
|
||||
typedef int int2 __attribute__((ext_vector_type(2)));
|
||||
typedef unsigned int uint2 __attribute__((ext_vector_type(2)));
|
||||
__nvvm_ldg_i2((const int2 *)p);
|
||||
__nvvm_ldg_ui2((const uint2 *)p);
|
||||
|
||||
// CHECK: call <4 x i32> @llvm.nvvm.ldg.global.i.v4i32.p0v4i32(<4 x i32>* {{%[0-9]+}}, i32 16)
|
||||
// CHECK: call <4 x i32> @llvm.nvvm.ldg.global.i.v4i32.p0v4i32(<4 x i32>* {{%[0-9]+}}, i32 16)
|
||||
typedef int int4 __attribute__((ext_vector_type(4)));
|
||||
typedef unsigned int uint4 __attribute__((ext_vector_type(4)));
|
||||
__nvvm_ldg_i4((const int4 *)p);
|
||||
__nvvm_ldg_ui4((const uint4 *)p);
|
||||
|
||||
// CHECK: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0v2i64(<2 x i64>* {{%[0-9]+}}, i32 16)
|
||||
// CHECK: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0v2i64(<2 x i64>* {{%[0-9]+}}, i32 16)
|
||||
typedef long long longlong2 __attribute__((ext_vector_type(2)));
|
||||
typedef unsigned long long ulonglong2 __attribute__((ext_vector_type(2)));
|
||||
__nvvm_ldg_ll2((const longlong2 *)p);
|
||||
__nvvm_ldg_ull2((const ulonglong2 *)p);
|
||||
|
||||
// CHECK: call <2 x float> @llvm.nvvm.ldg.global.f.v2f32.p0v2f32(<2 x float>* {{%[0-9]+}}, i32 8)
|
||||
typedef float float2 __attribute__((ext_vector_type(2)));
|
||||
__nvvm_ldg_f2((const float2 *)p);
|
||||
|
||||
// CHECK: call <4 x float> @llvm.nvvm.ldg.global.f.v4f32.p0v4f32(<4 x float>* {{%[0-9]+}}, i32 16)
|
||||
typedef float float4 __attribute__((ext_vector_type(4)));
|
||||
__nvvm_ldg_f4((const float4 *)p);
|
||||
|
||||
// CHECK: call <2 x double> @llvm.nvvm.ldg.global.f.v2f64.p0v2f64(<2 x double>* {{%[0-9]+}}, i32 16)
|
||||
typedef double double2 __attribute__((ext_vector_type(2)));
|
||||
__nvvm_ldg_d2((const double2 *)p);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue