maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[MIPS] Allow i1 values for 'r' constraint in inline-asm 

The bug was reported in the issue #52638.
This commit is contained in:
Simon Atanasyan 2021-12-13 19:16:39 +03:00
parent fb6b103daa
commit 2de9338587
2 changed files with 15 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -4121,7 +4121,7 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass);

14
llvm/test/CodeGen/Mips/inlineasm-constraint-r-i1.ll Normal file
View File

@ -0,0 +1,14 @@
; RUN: llc -mtriple=mips < %s | FileCheck %s
@a = global i8 0, align 1
define void @b() {
entry:
%0 = load i8, i8* @a, align 1
%tobool = trunc i8 %0 to i1
call void asm sideeffect "", "Jr,~{$1}"(i1 %tobool)
ret void
}
; CHECK: lui $1, %hi(a)
; CHECK-NEXT: lbu $2, %lo(a)($1)