From 2de1ddbd9c592c5297c6f02e52a472af2ed2ea3c Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Wed, 12 Jul 2017 14:48:27 +0000 Subject: [PATCH] [mips][mt][4/7] Add IAS support for dvpe, evpe instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793 --- llvm/lib/Target/Mips/MipsMTInstrFormats.td | 5 +++-- llvm/lib/Target/Mips/MipsMTInstrInfo.td | 22 +++++++++++++++++-- llvm/lib/Target/Mips/MipsSchedule.td | 4 ++++ llvm/lib/Target/Mips/MipsScheduleGeneric.td | 2 +- .../MC/Disassembler/Mips/mt/valid-r2-el.txt | 4 ++++ .../test/MC/Disassembler/Mips/mt/valid-r2.txt | 4 ++++ llvm/test/MC/Mips/mt/invalid.s | 6 +++++ llvm/test/MC/Mips/mt/valid.s | 5 +++++ 8 files changed, 47 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsMTInstrFormats.td b/llvm/lib/Target/Mips/MipsMTInstrFormats.td index 588b8cccb52d..81809cdf7606 100644 --- a/llvm/lib/Target/Mips/MipsMTInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsMTInstrFormats.td @@ -25,8 +25,8 @@ class OPCODE1 Val> { bits<1> Value = Val; } -def OPCODE_SC_DMT : OPCODE1<0b0>; -def OPCODE_SC_EMT : OPCODE1<0b1>; +def OPCODE_SC_D : OPCODE1<0b0>; +def OPCODE_SC_E : OPCODE1<0b1>; class FIELD5 Val> { bits<5> Value = Val; @@ -34,6 +34,7 @@ class FIELD5 Val> { def FIELD5_1_DMT_EMT : FIELD5<0b00001>; def FIELD5_2_DMT_EMT : FIELD5<0b01111>; +def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>; class COP0_MFMC0_MT : MipsMTInst { bits<32> Inst; diff --git a/llvm/lib/Target/Mips/MipsMTInstrInfo.td b/llvm/lib/Target/Mips/MipsMTInstrInfo.td index 54e1b25d4b8e..722024b8c0be 100644 --- a/llvm/lib/Target/Mips/MipsMTInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMTInstrInfo.td @@ -12,10 +12,16 @@ //===----------------------------------------------------------------------===// class DMT_ENC : COP0_MFMC0_MT; + OPCODE_SC_D>; class EMT_ENC : COP0_MFMC0_MT; + OPCODE_SC_E>; + +class DVPE_ENC : COP0_MFMC0_MT; + +class EVPE_ENC : COP0_MFMC0_MT; //===----------------------------------------------------------------------===// // MIPS MT Instruction Descriptions @@ -33,6 +39,10 @@ class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>; class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>; +class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>; + +class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>; + //===----------------------------------------------------------------------===// // MIPS MT Instruction Definitions //===----------------------------------------------------------------------===// @@ -41,6 +51,10 @@ let hasSideEffects = 1, isNotDuplicable = 1, def DMT : DMT_ENC, DMT_DESC, ASE_MT; def EMT : EMT_ENC, EMT_DESC, ASE_MT; + + def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT; + + def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT; } //===----------------------------------------------------------------------===// @@ -51,4 +65,8 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT; def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT; + + def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT; + + def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT; } diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td index 99fde2c159cc..cc64f3cc9e48 100644 --- a/llvm/lib/Target/Mips/MipsSchedule.td +++ b/llvm/lib/Target/Mips/MipsSchedule.td @@ -114,7 +114,9 @@ def II_DSBH : InstrItinClass; def II_DSHD : InstrItinClass; def II_DSUBU : InstrItinClass; def II_DSUB : InstrItinClass; +def II_DVPE : InstrItinClass; def II_EMT : InstrItinClass; +def II_EVPE : InstrItinClass; def II_EXT : InstrItinClass; // Any EXT instruction def II_FLOOR : InstrItinClass; def II_INS : InstrItinClass; // Any INS instruction @@ -407,7 +409,9 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, + InstrItinData]>, InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>, diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index c35d98f208e3..12e425146580 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -264,7 +264,7 @@ def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>; // MIPS MT instructions // ==================== -def : ItinRW<[GenericWriteMove], [II_DMT, II_EMT]>; +def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>; // MIPS32R6 and MIPS16e diff --git a/llvm/test/MC/Disassembler/Mips/mt/valid-r2-el.txt b/llvm/test/MC/Disassembler/Mips/mt/valid-r2-el.txt index ba020997dde7..7dc7414feb86 100644 --- a/llvm/test/MC/Disassembler/Mips/mt/valid-r2-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mt/valid-r2-el.txt @@ -3,4 +3,8 @@ 0xc1 0x0b 0x65 0x41 # CHECK: dmt $5 0xe1 0x0b 0x60 0x41 # CHECK: emt 0xe1 0x0b 0x64 0x41 # CHECK: emt $4 +0x01 0x00 0x60 0x41 # CHECK: dvpe +0x01 0x00 0x66 0x41 # CHECK: dvpe $6 +0x21 0x00 0x60 0x41 # CHECK: evpe +0x21 0x00 0x64 0x41 # CHECK: evpe $4 diff --git a/llvm/test/MC/Disassembler/Mips/mt/valid-r2.txt b/llvm/test/MC/Disassembler/Mips/mt/valid-r2.txt index 4a7d332dfd1d..8f0fdb038ce9 100644 --- a/llvm/test/MC/Disassembler/Mips/mt/valid-r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mt/valid-r2.txt @@ -3,4 +3,8 @@ 0x41 0x65 0x0b 0xc1 # CHECK: dmt $5 0x41 0x60 0x0b 0xe1 # CHECK: emt 0x41 0x64 0x0b 0xe1 # CHECK: emt $4 +0x41 0x60 0x00 0x01 # CHECK: dvpe +0x41 0x66 0x00 0x01 # CHECK: dvpe $6 +0x41 0x60 0x00 0x21 # CHECK: evpe +0x41 0x64 0x00 0x21 # CHECK: evpe $4 diff --git a/llvm/test/MC/Mips/mt/invalid.s b/llvm/test/MC/Mips/mt/invalid.s index b080702f4677..5a145a7e0850 100644 --- a/llvm/test/MC/Mips/mt/invalid.s +++ b/llvm/test/MC/Mips/mt/invalid.s @@ -5,3 +5,9 @@ emt 4 # CHECK: error: invalid operand for instruction emt $4, $5 # CHECK: error: invalid operand for instruction emt $5, 0($5) # CHECK: error: invalid operand for instruction + dvpe 4 # CHECK: error: invalid operand for instruction + dvpe $4, $5 # CHECK: error: invalid operand for instruction + dvpe $5, 0($4) # CHECK: error: invalid operand for instruction + evpe 4 # CHECK: error: invalid operand for instruction + evpe $4, $5 # CHECK: error: invalid operand for instruction + evpe $5, 0($5) # CHECK: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mt/valid.s b/llvm/test/MC/Mips/mt/valid.s index de8a0080b95b..d75304d46d4d 100644 --- a/llvm/test/MC/Mips/mt/valid.s +++ b/llvm/test/MC/Mips/mt/valid.s @@ -4,3 +4,8 @@ dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1] emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1] emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1] + dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01] + dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01] + evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21] + evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21] +