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[mips][mt][4/7] Add IAS support for dvpe, evpe instructions. 

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35251

llvm-svn: 307793
This commit is contained in:
Simon Dardis 2017-07-12 14:48:27 +00:00
parent 3e8a461bdf
commit 2de1ddbd9c
8 changed files with 47 additions and 5 deletions
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5
llvm/lib/Target/Mips/MipsMTInstrFormats.td
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@ -25,8 +25,8 @@ class OPCODE1<bits<1> Val> {
bits<1> Value = Val;
}
def OPCODE_SC_DMT : OPCODE1<0b0>;
def OPCODE_SC_EMT : OPCODE1<0b1>;
def OPCODE_SC_D : OPCODE1<0b0>;
def OPCODE_SC_E : OPCODE1<0b1>;
class FIELD5<bits<5> Val> {
bits<5> Value = Val;
@ -34,6 +34,7 @@ class FIELD5<bits<5> Val> {
def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
bits<32> Inst;

22
llvm/lib/Target/Mips/MipsMTInstrInfo.td
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@ -12,10 +12,16 @@
//===----------------------------------------------------------------------===//
class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
OPCODE_SC_DMT>;
OPCODE_SC_D>;
class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
OPCODE_SC_EMT>;
OPCODE_SC_E>;
class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
OPCODE_SC_D>;
class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
OPCODE_SC_E>;
//===----------------------------------------------------------------------===//
// MIPS MT Instruction Descriptions
@ -33,6 +39,10 @@ class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;
class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;
//===----------------------------------------------------------------------===//
// MIPS MT Instruction Definitions
//===----------------------------------------------------------------------===//
@ -41,6 +51,10 @@ let hasSideEffects = 1, isNotDuplicable = 1,
def DMT : DMT_ENC, DMT_DESC, ASE_MT;
def EMT : EMT_ENC, EMT_DESC, ASE_MT;
def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;
def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;
}
//===----------------------------------------------------------------------===//
@ -51,4 +65,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
}

4
llvm/lib/Target/Mips/MipsSchedule.td
View File

@ -114,7 +114,9 @@ def II_DSBH : InstrItinClass;
def II_DSHD : InstrItinClass;
def II_DSUBU : InstrItinClass;
def II_DSUB : InstrItinClass;
def II_DVPE : InstrItinClass;
def II_EMT : InstrItinClass;
def II_EVPE : InstrItinClass;
def II_EXT : InstrItinClass; // Any EXT instruction
def II_FLOOR : InstrItinClass;
def II_INS : InstrItinClass; // Any INS instruction
@ -407,7 +409,9 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_DSHD , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DVPE , [InstrStage<2, [ALU]>]>,
InstrItinData<II_EMT , [InstrStage<2, [ALU]>]>,
InstrItinData<II_EVPE , [InstrStage<2, [ALU]>]>,
InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,

2
llvm/lib/Target/Mips/MipsScheduleGeneric.td
View File

@ -264,7 +264,7 @@ def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>;
// MIPS MT instructions
// ====================
def : ItinRW<[GenericWriteMove], [II_DMT, II_EMT]>;
def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>;
// MIPS32R6 and MIPS16e

4
llvm/test/MC/Disassembler/Mips/mt/valid-r2-el.txt
View File

@ -3,4 +3,8 @@
0xc1 0x0b 0x65 0x41 # CHECK: dmt $5
0xe1 0x0b 0x60 0x41 # CHECK: emt
0xe1 0x0b 0x64 0x41 # CHECK: emt $4
0x01 0x00 0x60 0x41 # CHECK: dvpe
0x01 0x00 0x66 0x41 # CHECK: dvpe $6
0x21 0x00 0x60 0x41 # CHECK: evpe
0x21 0x00 0x64 0x41 # CHECK: evpe $4

4
llvm/test/MC/Disassembler/Mips/mt/valid-r2.txt
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@ -3,4 +3,8 @@
0x41 0x65 0x0b 0xc1 # CHECK: dmt $5
0x41 0x60 0x0b 0xe1 # CHECK: emt
0x41 0x64 0x0b 0xe1 # CHECK: emt $4
0x41 0x60 0x00 0x01 # CHECK: dvpe
0x41 0x66 0x00 0x01 # CHECK: dvpe $6
0x41 0x60 0x00 0x21 # CHECK: evpe
0x41 0x64 0x00 0x21 # CHECK: evpe $4

6
llvm/test/MC/Mips/mt/invalid.s
View File

@ -5,3 +5,9 @@
emt 4 # CHECK: error: invalid operand for instruction
emt $4, $5 # CHECK: error: invalid operand for instruction
emt $5, 0($5) # CHECK: error: invalid operand for instruction
dvpe 4 # CHECK: error: invalid operand for instruction
dvpe $4, $5 # CHECK: error: invalid operand for instruction
dvpe $5, 0($4) # CHECK: error: invalid operand for instruction
evpe 4 # CHECK: error: invalid operand for instruction
evpe $4, $5 # CHECK: error: invalid operand for instruction
evpe $5, 0($5) # CHECK: error: invalid operand for instruction

5
llvm/test/MC/Mips/mt/valid.s
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@ -4,3 +4,8 @@
dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]
emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]
dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]
dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]
evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]
evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]