forked from OSchip/llvm-project
[FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.
llvm-svn: 210610
This commit is contained in:
Juergen Ributzka
parent
d7e1fe40e1
commit
2dace6e54b
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@ -373,6 +373,9 @@ protected:
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/// - \c Add has a constant operand.
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bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
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/// Test whether the given value has exactly one use.
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bool hasTrivialKill(const Value *V) const;
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private:
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bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
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@ -408,9 +411,6 @@ private:
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/// beginning of the block. It helps to avoid spilling cached variables across
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/// heavy instructions like calls.
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void flushLocalValueMap();
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/// Test whether the given value has exactly one use.
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bool hasTrivialKill(const Value *V) const;
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};
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}
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@ -1637,6 +1637,18 @@ bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
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return true;
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}
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static bool isCommutativeIntrinsic(IntrinsicInst const &I) {
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switch (I.getIntrinsicID()) {
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::smul_with_overflow:
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case Intrinsic::umul_with_overflow:
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return true;
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default:
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return false;
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}
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}
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bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
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// FIXME: Handle more intrinsics.
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switch (I.getIntrinsicID()) {
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@ -1718,47 +1730,94 @@ bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
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return true;
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}
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow: {
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// FIXME: Should fold immediates.
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// Replace "add with overflow" intrinsics with an "add" instruction followed
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// by a seto/setc instruction.
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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case Intrinsic::smul_with_overflow:
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case Intrinsic::umul_with_overflow: {
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// This implements the basic lowering of the xalu with overflow intrinsics
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// into add/sub/mul folowed by either seto or setb.
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const Function *Callee = I.getCalledFunction();
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Type *RetTy =
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cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
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auto *Ty = cast<StructType>(Callee->getReturnType());
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Type *RetTy = Ty->getTypeAtIndex(0U);
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Type *CondTy = Ty->getTypeAtIndex(1);
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MVT VT;
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if (!isTypeLegal(RetTy, VT))
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return false;
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const Value *Op1 = I.getArgOperand(0);
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const Value *Op2 = I.getArgOperand(1);
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unsigned Reg1 = getRegForValue(Op1);
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unsigned Reg2 = getRegForValue(Op2);
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if (Reg1 == 0 || Reg2 == 0)
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// FIXME: Handle values *not* in registers.
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if (VT < MVT::i8 || VT > MVT::i64)
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return false;
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unsigned OpC = 0;
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if (VT == MVT::i32)
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OpC = X86::ADD32rr;
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else if (VT == MVT::i64)
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OpC = X86::ADD64rr;
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else
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const Value *LHS = I.getArgOperand(0);
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const Value *RHS = I.getArgOperand(1);
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// Canonicalize immediates to the RHS.
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if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
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isCommutativeIntrinsic(I))
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std::swap(LHS, RHS);
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unsigned BaseOpc, CondOpc;
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switch (I.getIntrinsicID()) {
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::sadd_with_overflow:
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BaseOpc = ISD::ADD; CondOpc = X86::SETOr; break;
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case Intrinsic::uadd_with_overflow:
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BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break;
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case Intrinsic::ssub_with_overflow:
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BaseOpc = ISD::SUB; CondOpc = X86::SETOr; break;
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case Intrinsic::usub_with_overflow:
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BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break;
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case Intrinsic::smul_with_overflow:
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BaseOpc = ISD::MUL; CondOpc = X86::SETOr; break;
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case Intrinsic::umul_with_overflow:
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BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break;
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}
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unsigned LHSReg = getRegForValue(LHS);
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if (LHSReg == 0)
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return false;
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bool LHSIsKill = hasTrivialKill(LHS);
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unsigned ResultReg = 0;
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// Check if we have an immediate version.
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if (auto const *C = dyn_cast<ConstantInt>(RHS)) {
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ResultReg = FastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill,
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C->getZExtValue());
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}
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unsigned RHSReg;
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bool RHSIsKill;
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if (!ResultReg) {
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RHSReg = getRegForValue(RHS);
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if (RHSReg == 0)
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return false;
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RHSIsKill = hasTrivialKill(RHS);
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ResultReg = FastEmit_rr(VT, VT, BaseOpc, LHSReg, LHSIsKill, RHSReg,
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RHSIsKill);
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}
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// FastISel doesn't have a pattern for X86::MUL*r. Emit it manually.
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if (BaseOpc == X86ISD::UMUL && !ResultReg) {
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static const unsigned MULOpc[] =
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{ X86::MUL8r, X86::MUL16r, X86::MUL32r, X86::MUL64r };
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static const unsigned Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
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// First copy the first operand into RAX, which is an implicit input to
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// the X86::MUL*r instruction.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8])
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.addReg(LHSReg, getKillRegState(LHSIsKill));
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ResultReg = FastEmitInst_r(MULOpc[VT.SimpleTy-MVT::i8],
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TLI.getRegClassFor(VT), RHSReg, RHSIsKill);
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}
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if (!ResultReg)
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return false;
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// The call to CreateRegs builds two sequential registers, to store the
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// both the returned values.
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unsigned ResultReg = FuncInfo.CreateRegs(I.getType());
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpC), ResultReg)
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.addReg(Reg1).addReg(Reg2);
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unsigned Opc = X86::SETBr;
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if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
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Opc = X86::SETOr;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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ResultReg + 1);
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unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
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assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
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ResultReg2);
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UpdateValueMap(&I, ResultReg, 2);
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return true;
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@ -0,0 +1,337 @@
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; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s -check-prefix=DAG
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; RUN: llc -mtriple=x86_64-unknown-unknown -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=FAST
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;
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; Get the actual value of the overflow bit.
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;
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; SADDO reg, reg
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define zeroext i1 @saddo.i8(i8 signext %v1, i8 signext %v2, i8* %res) {
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entry:
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; DAG-LABEL: saddo.i8
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; DAG: addb %sil, %dil
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i8
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; FAST: addb %sil, %dil
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; FAST-NEXT: seto %al
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%t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 %v2)
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%val = extractvalue {i8, i1} %t, 0
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%obit = extractvalue {i8, i1} %t, 1
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store i8 %val, i8* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.i16(i16 %v1, i16 %v2, i16* %res) {
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entry:
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; DAG-LABEL: saddo.i16
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; DAG: addw %si, %di
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i16
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; FAST: addw %si, %di
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; FAST-NEXT: seto %al
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%t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 %v2)
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%val = extractvalue {i16, i1} %t, 0
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%obit = extractvalue {i16, i1} %t, 1
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store i16 %val, i16* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; DAG-LABEL: saddo.i32
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; DAG: addl %esi, %edi
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i32
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; FAST: addl %esi, %edi
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; FAST-NEXT: seto %al
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64
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; DAG: addq %rsi, %rdi
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i64
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; FAST: addq %rsi, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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; SADDO reg, imm | imm, reg
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; FIXME: INC isn't supported in FastISel yet
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define zeroext i1 @saddo.i64imm1(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm1
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; DAG: incq %rdi
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i64imm1
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; FAST: addq $1, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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; FIXME: DAG doesn't optimize immediates on the LHS.
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define zeroext i1 @saddo.i64imm2(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm2
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; DAG: mov
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; DAG-NEXT: addq
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm2
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; FAST: addq $1, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 1, i64 %v1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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; Check boundary conditions for large immediates.
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define zeroext i1 @saddo.i64imm3(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm3
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; DAG: addq $-2147483648, %rdi
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i64imm3
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; FAST: addq $-2147483648, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -2147483648)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.i64imm4(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm4
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; DAG: movabsq $-21474836489, %[[REG:[a-z]+]]
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; DAG-NEXT: addq %rdi, %[[REG]]
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm4
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; FAST: movabsq $-21474836489, %[[REG:[a-z]+]]
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; FAST-NEXT: addq %rdi, %[[REG]]
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; FAST-NEXT: seto
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -21474836489)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.i64imm5(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm5
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; DAG: addq $2147483647, %rdi
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm5
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; FAST: addq $2147483647, %rdi
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; FAST-NEXT: seto
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483647)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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; TODO: FastISel shouldn't use movabsq.
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define zeroext i1 @saddo.i64imm6(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm6
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; DAG: movl $2147483648, %ecx
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; DAG: addq %rdi, %rcx
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm6
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; FAST: movabsq $2147483648, %[[REG:[a-z]+]]
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; FAST: addq %rdi, %[[REG]]
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; FAST-NEXT: seto
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483648)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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; UADDO
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define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; DAG-LABEL: uaddo.i32
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; DAG: addl %esi, %edi
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; DAG-NEXT: setb %al
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; FAST-LABEL: uaddo.i32
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; FAST: addl %esi, %edi
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; FAST-NEXT: setb %al
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; DAG-LABEL: uaddo.i64
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; DAG: addq %rsi, %rdi
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; DAG-NEXT: setb %al
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; FAST-LABEL: uaddo.i64
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; FAST: addq %rsi, %rdi
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; FAST-NEXT: setb %al
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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; SSUBO
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define zeroext i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; DAG-LABEL: ssubo.i32
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; DAG: subl %esi, %edi
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; DAG-NEXT: seto %al
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; FAST-LABEL: ssubo.i32
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; FAST: subl %esi, %edi
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; FAST-NEXT: seto %al
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; DAG-LABEL: ssubo.i64
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; DAG: subq %rsi, %rdi
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; DAG-NEXT: seto %al
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; FAST-LABEL: ssubo.i64
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; FAST: subq %rsi, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
|
||||
%val = extractvalue {i64, i1} %t, 0
|
||||
%obit = extractvalue {i64, i1} %t, 1
|
||||
store i64 %val, i64* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
; USUBO
|
||||
define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
|
||||
entry:
|
||||
; DAG-LABEL: usubo.i32
|
||||
; DAG: subl %esi, %edi
|
||||
; DAG-NEXT: setb %al
|
||||
; FAST-LABEL: usubo.i32
|
||||
; FAST: subl %esi, %edi
|
||||
; FAST-NEXT: setb %al
|
||||
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
|
||||
%val = extractvalue {i32, i1} %t, 0
|
||||
%obit = extractvalue {i32, i1} %t, 1
|
||||
store i32 %val, i32* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
|
||||
entry:
|
||||
; DAG-LABEL: usubo.i64
|
||||
; DAG: subq %rsi, %rdi
|
||||
; DAG-NEXT: setb %al
|
||||
; FAST-LABEL: usubo.i64
|
||||
; FAST: subq %rsi, %rdi
|
||||
; FAST-NEXT: setb %al
|
||||
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
|
||||
%val = extractvalue {i64, i1} %t, 0
|
||||
%obit = extractvalue {i64, i1} %t, 1
|
||||
store i64 %val, i64* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
; SMULO
|
||||
define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
|
||||
entry:
|
||||
; DAG-LABEL: smulo.i32
|
||||
; DAG: imull %esi, %edi
|
||||
; DAG-NEXT: seto %al
|
||||
; FAST-LABEL: smulo.i32
|
||||
; FAST: imull %esi, %edi
|
||||
; FAST-NEXT: seto %al
|
||||
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
||||
%val = extractvalue {i32, i1} %t, 0
|
||||
%obit = extractvalue {i32, i1} %t, 1
|
||||
store i32 %val, i32* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
|
||||
entry:
|
||||
; DAG-LABEL: smulo.i64
|
||||
; DAG: imulq %rsi, %rdi
|
||||
; DAG-NEXT: seto %al
|
||||
; FAST-LABEL: smulo.i64
|
||||
; FAST: imulq %rsi, %rdi
|
||||
; FAST-NEXT: seto %al
|
||||
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
||||
%val = extractvalue {i64, i1} %t, 0
|
||||
%obit = extractvalue {i64, i1} %t, 1
|
||||
store i64 %val, i64* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
; UMULO
|
||||
define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
|
||||
entry:
|
||||
; DAG-LABEL: umulo.i32
|
||||
; DAG: mull %esi
|
||||
; DAG-NEXT: seto
|
||||
; FAST-LABEL: umulo.i32
|
||||
; FAST: mull %esi
|
||||
; FAST-NEXT: seto
|
||||
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
||||
%val = extractvalue {i32, i1} %t, 0
|
||||
%obit = extractvalue {i32, i1} %t, 1
|
||||
store i32 %val, i32* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
|
||||
entry:
|
||||
; DAG-LABEL: umulo.i64
|
||||
; DAG: mulq %rsi
|
||||
; DAG-NEXT: seto
|
||||
; FAST-LABEL: umulo.i64
|
||||
; FAST: mulq %rsi
|
||||
; FAST-NEXT: seto
|
||||
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
||||
%val = extractvalue {i64, i1} %t, 0
|
||||
%obit = extractvalue {i64, i1} %t, 1
|
||||
store i64 %val, i64* %res
|
||||
ret i1 %obit
|
||||
}
|
||||
|
||||
declare {i8, i1} @llvm.sadd.with.overflow.i8(i8, i8) nounwind readnone
|
||||
declare {i16, i1} @llvm.sadd.with.overflow.i16(i16, i16) nounwind readnone
|
||||
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
|
||||
declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
|
||||
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
|
||||
declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
|
||||
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
|
||||
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
|
||||
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
|
||||
declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
|
||||
declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
|
||||
declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
|
||||
declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
|
||||
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
|
||||
|
||||
Loading…
Reference in New Issue