forked from OSchip/llvm-project
[mips][microMIPS] Implement LLE, LUI, LW and LWE instructions
Differential Revision: http://reviews.llvm.org/D1179 llvm-svn: 247017
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@ -254,6 +254,48 @@ class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
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let Inst{8-0} = offset;
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}
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class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = 0b011000;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-12} = 0b0110;
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let Inst{11-9} = funct;
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let Inst{8-0} = offset;
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}
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class LOAD_WORD_FM_MMR6 {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<16> offset = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b111111;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-0} = offset;
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}
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class LOAD_UPPER_IMM_FM_MMR6 {
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = 0b000100;
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let Inst{25-21} = rt;
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let Inst{20-16} = 0;
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let Inst{15-0} = imm16;
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}
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class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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@ -104,6 +104,10 @@ class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
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class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
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class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
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class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
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class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
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class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
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class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
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class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
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class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd>
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@ -637,6 +641,39 @@ class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
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class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
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class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
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class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
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MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs RO:$rt);
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dag InOperandList = (ins mem_mm_12:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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string DecoderMethod = "DecodeMemMMImm9";
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bit mayLoad = 1;
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}
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class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
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class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
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class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins mem:$addr);
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string AsmString = "lw\t$rt, $addr";
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let DecoderMethod = "DecodeMemMMImm16";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
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InstrItinClass Itinerary = II_LW;
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}
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class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins uimm16:$imm16);
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string AsmString = "lui\t$rt, $imm16";
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list<dag> Pattern = [];
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bit hasSideEffects = 0;
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bit isReMaterializable = 1;
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InstrItinClass Itinerary = II_LUI;
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Format Form = FrmI;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -825,6 +862,10 @@ def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
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def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
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def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
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def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
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def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
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def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
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def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
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def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
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}
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//===----------------------------------------------------------------------===//
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@ -1225,7 +1225,7 @@ def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
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LW_FM<0x21>;
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def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
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def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
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LW_FM<0x23>;
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}
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def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
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@ -142,6 +142,14 @@
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0x60 0x85 0xaa 0x06 # CHECK: she $4, 6($5)
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0x60 0x85 0x6c 0x06 # CHECK: lle $4, 6($5)
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0x60 0x85 0x6e 0x06 # CHECK: lwe $4, 6($5)
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0xfc 0x85 0x00 0x06 # CHECK: lw $4, 6($5)
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0x10 0xc0 0x45 0x67 # CHECK: lui $6, 17767
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0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4
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0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
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@ -168,4 +168,8 @@
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sce $4, 6($5) # CHECK: sce $4, 6($5) # encoding: [0x60,0x85,0xac,0x06]
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sh $4, 6($5) # CHECK: sh $4, 6($5) # encoding: [0x38,0x85,0x00,0x06]
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she $4, 6($5) # CHECK: she $4, 6($5) # encoding: [0x60,0x85,0xaa,0x06]
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lle $4, 6($5) # CHECK: lle $4, 6($5) # encoding: [0x60,0x85,0x6c,0x06]
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lwe $4, 6($5) # CHECK: lwe $4, 6($5) # encoding: [0x60,0x85,0x6e,0x06]
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lw $4, 6($5) # CHECK: lw $4, 6($5) # encoding: [0xfc,0x85,0x00,0x06]
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lui $6, 17767 # CHECK: lui $6, 17767 # encoding: [0x10,0xc0,0x45,0x67]
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