forked from OSchip/llvm-project
[AArch64] Handle ST1iN instructions in isAArch64FrameOffsetLegal
Before the code would crash with "unhandled opcode in isAArch64FrameOffsetLegal" when there was a spill from extractelement. Fixes pr52249 Differential Revision: https://reviews.llvm.org/D112311
This commit is contained in:
Danila Malyutin
parent
40e4ac3e5b
commit
2d9ee590b6
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@ -4288,6 +4288,10 @@ int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI,
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case AArch64::ST1Twov1d:
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case AArch64::ST1Threev1d:
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case AArch64::ST1Fourv1d:
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case AArch64::ST1i8:
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case AArch64::ST1i16:
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case AArch64::ST1i32:
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case AArch64::ST1i64:
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case AArch64::IRG:
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case AArch64::IRGstack:
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case AArch64::STGloop:
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@ -0,0 +1,110 @@
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# Check that it doesn't crash with unhandled opcode error, see pr52249
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass localstackalloc -o - %s | FileCheck %s
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--- |
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define void @test_st1_to_sp(<2 x i32> %a, <4 x i16> %b, <8 x i8> %c, <2 x i64> %d) gc "statepoint-example" { entry: ret void }
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...
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---
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# CHECK-LABEL: test_st1_to_sp
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name: test_st1_to_sp
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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failsVerification: false
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registers:
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- { id: 0, class: fpr64, preferred-register: '' }
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- { id: 1, class: fpr64, preferred-register: '' }
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- { id: 2, class: fpr64, preferred-register: '' }
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- { id: 3, class: fpr128, preferred-register: '' }
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- { id: 4, class: fpr64, preferred-register: '' }
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- { id: 5, class: fpr128, preferred-register: '' }
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- { id: 6, class: fpr128, preferred-register: '' }
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- { id: 7, class: fpr64, preferred-register: '' }
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- { id: 8, class: fpr128, preferred-register: '' }
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- { id: 9, class: fpr128, preferred-register: '' }
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- { id: 10, class: fpr64, preferred-register: '' }
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- { id: 11, class: fpr128, preferred-register: '' }
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- { id: 12, class: fpr128, preferred-register: '' }
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- { id: 13, class: fpr128, preferred-register: '' }
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- { id: 14, class: gpr32all, preferred-register: '' }
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- { id: 15, class: gpr64all, preferred-register: '' }
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liveins:
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- { reg: '$d0', virtual-reg: '%0' }
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- { reg: '$d1', virtual-reg: '%1' }
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- { reg: '$d2', virtual-reg: '%2' }
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- { reg: '$q3', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 8
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adjustsStack: true
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: default, offset: 0, size: 2, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: default, offset: 0, size: 1, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $d0, $d1, $d2, $q3
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%3:fpr128 = COPY $q3
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%2:fpr64 = COPY $d2
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%1:fpr64 = COPY $d1
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%0:fpr64 = COPY $d0
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%4:fpr64 = SSHRv2i32_shift %0, 1
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%6:fpr128 = IMPLICIT_DEF
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%5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub
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%7:fpr64 = SSHRv4i16_shift %1, 1
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%9:fpr128 = IMPLICIT_DEF
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%8:fpr128 = INSERT_SUBREG %9, killed %7, %subreg.dsub
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%10:fpr64 = SSHRv8i8_shift %2, 1
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%12:fpr128 = IMPLICIT_DEF
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%11:fpr128 = INSERT_SUBREG %12, killed %10, %subreg.dsub
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%13:fpr128 = SSHRv2i64_shift %3, 1
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ST1i64 killed %13, 1, %stack.3 :: (store (s64) into %stack.3)
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ST1i16 killed %8, 1, %stack.1 :: (store (s16) into %stack.1, align 4)
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ST1i32 killed %5, 1, %stack.0 :: (store (s32) into %stack.0)
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ST1i8 killed %11, 1, %stack.2 :: (store (s8) into %stack.2, align 4)
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ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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%14:gpr32all = IMPLICIT_DEF
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$w0 = COPY %14
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%15:gpr64all = IMPLICIT_DEF
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STATEPOINT 2, 4, 1, killed %15, $w0, 2, 0, 2, 0, 2, 4, 1, 4, %stack.0, 0, 1, 2, %stack.1, 0, 1, 1, %stack.2, 0, 1, 8, %stack.3, 0, 2, 0, 2, 0, 2, 0, csr_aarch64_aapcs, implicit-def $sp :: (volatile load store (s32) on %stack.0), (volatile load store (s16) on %stack.1, align 4), (volatile load store (s8) on %stack.2, align 4), (volatile load store (s64) on %stack.3)
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ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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RET_ReallyLR
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...
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