forked from OSchip/llvm-project
[X86] Use DAG::getBuildVector helper wrapper where possible. NFCI.
llvm-svn: 284835
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0ff17b627d
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@ -4463,8 +4463,8 @@ static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
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// If the input is a buildvector just emit a smaller one.
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if (Vec.getOpcode() == ISD::BUILD_VECTOR)
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return DAG.getNode(ISD::BUILD_VECTOR,
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dl, ResultVT, makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
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return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
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makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
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SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
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@ -19419,7 +19419,7 @@ static SDValue LowerVectorCTLZInRegLUT(SDValue Op, const SDLoc &DL,
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SmallVector<SDValue, 64> LUTVec;
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for (int i = 0; i < NumBytes; ++i)
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LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
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SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, CurrVT, LUTVec);
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SDValue InRegLUT = DAG.getBuildVector(CurrVT, DL, LUTVec);
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// Begin by bitcasting the input to byte vector, then split those bytes
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// into lo/hi nibbles and use the PSHUFB LUT to perform CLTZ on each of them.
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@ -31779,7 +31779,7 @@ static SDValue combineVZext(SDNode *N, SelectionDAG &DAG,
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Cst = Cst.zextOrTrunc(SVT.getSizeInBits());
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Vals.push_back(DAG.getConstant(Cst, DL, SVT));
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}
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Vals);
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return DAG.getBuildVector(VT, DL, Vals);
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}
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// (vzext (bitcast (vzext (x)) -> (vzext x)
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