forked from OSchip/llvm-project
[LSR] add testcase for LSR profitable chain change, nfc
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Chen Zheng
parent
8156074352
commit
2d71f26c81
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@ -0,0 +1,211 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s
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define void @foo(double* readonly %0, double* %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpd 5, 7
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; CHECK-NEXT: std 23, -72(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 24, -64(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 25, -56(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 26, -48(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 27, -40(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 28, -32(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: bge 0, .LBB0_6
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; CHECK-NEXT: # %bb.1: # %.preheader
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; CHECK-NEXT: mulld 11, 8, 5
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; CHECK-NEXT: mulld 12, 9, 8
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; CHECK-NEXT: sldi 0, 10, 3
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; CHECK-NEXT: sldi 11, 11, 3
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; CHECK-NEXT: sldi 12, 12, 3
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; CHECK-NEXT: add 11, 3, 11
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: add 5, 5, 9
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; CHECK-NEXT: add 11, 11, 12
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; CHECK-NEXT: cmpd 5, 7
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; CHECK-NEXT: bge 0, .LBB0_6
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; CHECK-NEXT: .LBB0_3: # =>This Loop Header: Depth=1
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; CHECK-NEXT: # Child Loop BB0_5 Depth 2
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; CHECK-NEXT: sub 30, 5, 10
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; CHECK-NEXT: cmpd 6, 30
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; CHECK-NEXT: bge 0, .LBB0_2
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; CHECK-NEXT: # %bb.4:
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; CHECK-NEXT: addi 28, 5, 1
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; CHECK-NEXT: addi 27, 5, 2
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; CHECK-NEXT: addi 26, 5, 3
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; CHECK-NEXT: mulld 29, 5, 8
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; CHECK-NEXT: sldi 25, 6, 3
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; CHECK-NEXT: mulld 28, 28, 8
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; CHECK-NEXT: mulld 27, 27, 8
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; CHECK-NEXT: mulld 26, 26, 8
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_5: # Parent Loop BB0_3 Depth=1
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; CHECK-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-NEXT: lfdx 0, 4, 25
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; CHECK-NEXT: lfdx 1, 11, 25
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; CHECK-NEXT: add 24, 6, 29
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; CHECK-NEXT: mr 23, 3
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: sldi 24, 24, 3
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; CHECK-NEXT: add 24, 3, 24
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; CHECK-NEXT: lfd 1, 8(24)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 16(24)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 24(24)
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; CHECK-NEXT: add 24, 6, 28
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; CHECK-NEXT: sldi 24, 24, 3
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfdux 1, 23, 24
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; CHECK-NEXT: add 24, 6, 27
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; CHECK-NEXT: sldi 24, 24, 3
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 8(23)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 16(23)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 24(23)
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; CHECK-NEXT: mr 23, 3
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; CHECK-NEXT: lfdux 2, 23, 24
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; CHECK-NEXT: add 24, 6, 26
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; CHECK-NEXT: add 6, 6, 10
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; CHECK-NEXT: sldi 24, 24, 3
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; CHECK-NEXT: cmpd 6, 30
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 8(23)
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; CHECK-NEXT: xsadddp 0, 0, 2
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 16(23)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 24(23)
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; CHECK-NEXT: mr 23, 3
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfdux 1, 23, 24
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 8(23)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 16(23)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: lfd 1, 24(23)
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; CHECK-NEXT: xsadddp 0, 0, 1
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; CHECK-NEXT: stfdx 0, 4, 25
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; CHECK-NEXT: add 25, 25, 0
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; CHECK-NEXT: blt 0, .LBB0_5
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_6:
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 28, -32(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 27, -40(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 26, -48(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 25, -56(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 24, -64(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 23, -72(1) # 8-byte Folded Reload
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; CHECK-NEXT: blr
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%9 = icmp slt i64 %2, %4
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br i1 %9, label %10, label %97
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10: ; preds = %8, %93
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%11 = phi i64 [ %95, %93 ], [ %2, %8 ]
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%12 = phi i64 [ %94, %93 ], [ %3, %8 ]
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%13 = sub nsw i64 %11, %7
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%14 = icmp slt i64 %12, %13
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br i1 %14, label %15, label %93
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15: ; preds = %10
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%16 = mul nsw i64 %11, %5
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%17 = add nsw i64 %11, 1
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%18 = mul nsw i64 %17, %5
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%19 = add nsw i64 %11, 2
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%20 = mul nsw i64 %19, %5
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%21 = add nsw i64 %11, 3
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%22 = mul nsw i64 %21, %5
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br label %23
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23: ; preds = %15, %23
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%24 = phi i64 [ %12, %15 ], [ %91, %23 ]
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%25 = getelementptr inbounds double, double* %1, i64 %24
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%26 = load double, double* %25, align 8
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%27 = add nsw i64 %24, %16
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%28 = getelementptr inbounds double, double* %0, i64 %27
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%29 = load double, double* %28, align 8
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%30 = fadd double %26, %29
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%31 = add nsw i64 %27, 1
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%32 = getelementptr inbounds double, double* %0, i64 %31
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%33 = load double, double* %32, align 8
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%34 = fadd double %30, %33
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%35 = add nsw i64 %27, 2
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%36 = getelementptr inbounds double, double* %0, i64 %35
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%37 = load double, double* %36, align 8
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%38 = fadd double %34, %37
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%39 = add nsw i64 %27, 3
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%40 = getelementptr inbounds double, double* %0, i64 %39
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%41 = load double, double* %40, align 8
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%42 = fadd double %38, %41
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%43 = add nsw i64 %24, %18
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%44 = getelementptr inbounds double, double* %0, i64 %43
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%45 = load double, double* %44, align 8
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%46 = fadd double %42, %45
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%47 = add nsw i64 %43, 1
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%48 = getelementptr inbounds double, double* %0, i64 %47
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%49 = load double, double* %48, align 8
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%50 = fadd double %46, %49
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%51 = add nsw i64 %43, 2
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%52 = getelementptr inbounds double, double* %0, i64 %51
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%53 = load double, double* %52, align 8
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%54 = fadd double %50, %53
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%55 = add nsw i64 %43, 3
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%56 = getelementptr inbounds double, double* %0, i64 %55
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%57 = load double, double* %56, align 8
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%58 = fadd double %54, %57
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%59 = add nsw i64 %24, %20
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%60 = getelementptr inbounds double, double* %0, i64 %59
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%61 = load double, double* %60, align 8
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%62 = fadd double %58, %61
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%63 = add nsw i64 %59, 1
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%64 = getelementptr inbounds double, double* %0, i64 %63
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%65 = load double, double* %64, align 8
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%66 = fadd double %62, %65
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%67 = add nsw i64 %59, 2
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%68 = getelementptr inbounds double, double* %0, i64 %67
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%69 = load double, double* %68, align 8
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%70 = fadd double %66, %69
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%71 = add nsw i64 %59, 3
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%72 = getelementptr inbounds double, double* %0, i64 %71
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%73 = load double, double* %72, align 8
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%74 = fadd double %70, %73
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%75 = add nsw i64 %24, %22
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%76 = getelementptr inbounds double, double* %0, i64 %75
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%77 = load double, double* %76, align 8
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%78 = fadd double %74, %77
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%79 = add nsw i64 %75, 1
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%80 = getelementptr inbounds double, double* %0, i64 %79
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%81 = load double, double* %80, align 8
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%82 = fadd double %78, %81
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%83 = add nsw i64 %75, 2
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%84 = getelementptr inbounds double, double* %0, i64 %83
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%85 = load double, double* %84, align 8
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%86 = fadd double %82, %85
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%87 = add nsw i64 %75, 3
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%88 = getelementptr inbounds double, double* %0, i64 %87
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%89 = load double, double* %88, align 8
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%90 = fadd double %86, %89
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store double %90, double* %25, align 8
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%91 = add nsw i64 %24, %7
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%92 = icmp slt i64 %91, %13
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br i1 %92, label %23, label %93
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93: ; preds = %23, %10
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%94 = phi i64 [ %12, %10 ], [ %91, %23 ]
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%95 = add nsw i64 %11, %6
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%96 = icmp slt i64 %95, %4
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br i1 %96, label %10, label %97
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97: ; preds = %93, %8
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ret void
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}
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