forked from OSchip/llvm-project
A target definition file that may work for
Aarch32 Cortex-M target processor debugging. <rdar://problem/48448564> llvm-svn: 356416
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Jason Molenda
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#!/usr/bin/python
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#===-- armv7_cortex_m_target_definition.py.py ------------------*- C++ -*-===//
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#
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# The LLVM Compiler Infrastructure
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#
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# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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# See https://llvm.org/LICENSE.txt for license information.
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# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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#
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#===----------------------------------------------------------------------===//
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#----------------------------------------------------------------------
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# DESCRIPTION
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#
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# This file can be used with the following setting:
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# plugin.process.gdb-remote.target-definition-file
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# This setting should be used when you are trying to connect to a
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# remote GDB server that doesn't support any of the register discovery
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# packets that LLDB normally uses.
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#
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# Why is this necessary? LLDB doesn't require a new build of LLDB that
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# targets each new architecture you will debug with. Instead, all
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# architectures are supported and LLDB relies on extra GDB server
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# packets to discover the target we are connecting to so that is can
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# show the right registers for each target. This allows the GDB server
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# to change and add new registers without requiring a new LLDB build
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# just so we can see new registers.
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#
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# This file implements the x86_64 registers for the darwin version of
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# GDB and allows you to connect to servers that use this register set.
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#
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# USAGE
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#
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# (lldb) settings set plugin.process.gdb-remote.target-definition-file /path/to/armv7_cortex_m_target_defintion.py
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# (lldb) gdb-remote other.baz.com:1234
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#
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# The target definition file will get used if and only if the
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# qRegisterInfo packets are not supported when connecting to a remote
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# GDB server.
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#----------------------------------------------------------------------
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from lldb import *
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# DWARF register numbers
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name_to_dwarf_regnum = {
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'r0' : 0 ,
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'r1' : 1 ,
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'r2' : 2 ,
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'r3' : 3 ,
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'r4' : 4 ,
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'r5' : 5 ,
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'r6' : 6 ,
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'r7' : 7 ,
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'r9' : 8 ,
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'r10' : 9 ,
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'r11' : 10,
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'r12' : 11,
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'sp' : 12,
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'lr' : 13,
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'pc' : 14,
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'r15' : 15,
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'xpsr' : 16,
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};
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name_to_generic_regnum = {
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'pc' : LLDB_REGNUM_GENERIC_PC,
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'sp' : LLDB_REGNUM_GENERIC_SP,
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'r7' : LLDB_REGNUM_GENERIC_FP,
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'lr' : LLDB_REGNUM_GENERIC_RA,
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'r0' : LLDB_REGNUM_GENERIC_ARG1,
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'r1' : LLDB_REGNUM_GENERIC_ARG2,
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'r2' : LLDB_REGNUM_GENERIC_ARG3,
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'r3' : LLDB_REGNUM_GENERIC_ARG4
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};
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def get_reg_num (reg_num_dict, reg_name):
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if reg_name in reg_num_dict:
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return reg_num_dict[reg_name]
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return LLDB_INVALID_REGNUM
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def get_reg_num (reg_num_dict, reg_name):
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if reg_name in reg_num_dict:
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return reg_num_dict[reg_name]
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return LLDB_INVALID_REGNUM
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armv7_register_infos = [
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{ 'name':'r0' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg1' },
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{ 'name':'r1' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg2' },
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{ 'name':'r2' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg3' },
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{ 'name':'r3' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg4' },
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{ 'name':'r4' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r5' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r6' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r7' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'fp' },
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{ 'name':'r8' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r9' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r10' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r11' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'r12' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo },
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{ 'name':'sp' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'r13' },
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{ 'name':'lr' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'r14' },
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{ 'name':'pc' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'r15' },
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{ 'name':'xpsr' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'cpsr' },
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];
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g_target_definition = None
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def get_target_definition ():
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global g_target_definition
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if g_target_definition == None:
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g_target_definition = {}
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offset = 0
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for reg_info in armv7_register_infos:
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reg_name = reg_info['name']
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if 'slice' not in reg_info and 'composite' not in reg_info:
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reg_info['offset'] = offset
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offset += reg_info['bitsize'] / 8
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# Set the DWARF/eh_frame register number for this register if it has one
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reg_num = get_reg_num(name_to_dwarf_regnum, reg_name)
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if reg_num != LLDB_INVALID_REGNUM:
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reg_info['gcc'] = reg_num
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reg_info['ehframe'] = reg_num
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# Set the generic register number for this register if it has one
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reg_num = get_reg_num(name_to_generic_regnum, reg_name)
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if reg_num != LLDB_INVALID_REGNUM:
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reg_info['generic'] = reg_num
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g_target_definition['sets'] = ['General Purpose Registers']
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g_target_definition['registers'] = armv7_register_infos
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g_target_definition['host-info'] = { 'triple' : 'armv7em--', 'endian': eByteOrderLittle }
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g_target_definition['g-packet-size'] = offset
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return g_target_definition
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def get_dynamic_setting(target, setting_name):
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if setting_name == 'gdb-server-target-definition':
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return get_target_definition()
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