forked from OSchip/llvm-project
[X86] Add PreprocessISelDAG support for turning ISD::FP_TO_SINT/UINT into X86ISD::CVTTP2SI/CVTTP2UI and to reduce the number of isel patterns.
llvm-svn: 364887
This commit is contained in:
Craig Topper
parent
7fdb3a293b
commit
2d306b2d57
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@ -792,6 +792,27 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
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}
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switch (N->getOpcode()) {
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT: {
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// Replace vector fp_to_s/uint with their X86 specific equivalent so we
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// don't need 2 sets of patterns.
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if (!N->getSimpleValueType(0).isVector())
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break;
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unsigned NewOpc;
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switch (N->getOpcode()) {
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default: llvm_unreachable("Unexpected opcode!");
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case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break;
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case ISD::FP_TO_UINT: NewOpc = X86ISD::CVTTP2UI; break;
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}
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SDValue Res = CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0),
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N->getOperand(0));
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--I;
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
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++I;
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CurDAG->DeleteNode(N);
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continue;
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}
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL: {
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@ -8173,59 +8173,7 @@ defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
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X86VUintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, XD,
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EVEX_CD8<64, CD8VF>;
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let Predicates = [HasAVX512] in {
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def : Pat<(v16i32 (fp_to_sint (v16f32 VR512:$src))),
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(VCVTTPS2DQZrr VR512:$src)>;
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def : Pat<(v16i32 (fp_to_sint (loadv16f32 addr:$src))),
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(VCVTTPS2DQZrm addr:$src)>;
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def : Pat<(v16i32 (fp_to_uint (v16f32 VR512:$src))),
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(VCVTTPS2UDQZrr VR512:$src)>;
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def : Pat<(v16i32 (fp_to_uint (loadv16f32 addr:$src))),
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(VCVTTPS2UDQZrm addr:$src)>;
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def : Pat<(v8i32 (fp_to_sint (v8f64 VR512:$src))),
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(VCVTTPD2DQZrr VR512:$src)>;
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def : Pat<(v8i32 (fp_to_sint (loadv8f64 addr:$src))),
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(VCVTTPD2DQZrm addr:$src)>;
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def : Pat<(v8i32 (fp_to_uint (v8f64 VR512:$src))),
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(VCVTTPD2UDQZrr VR512:$src)>;
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def : Pat<(v8i32 (fp_to_uint (loadv8f64 addr:$src))),
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(VCVTTPD2UDQZrm addr:$src)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(v4i32 (fp_to_sint (v4f32 VR128X:$src))),
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(VCVTTPS2DQZ128rr VR128X:$src)>;
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def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
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(VCVTTPS2DQZ128rm addr:$src)>;
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def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src))),
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(VCVTTPS2UDQZ128rr VR128X:$src)>;
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def : Pat<(v4i32 (fp_to_uint (loadv4f32 addr:$src))),
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(VCVTTPS2UDQZ128rm addr:$src)>;
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def : Pat<(v8i32 (fp_to_sint (v8f32 VR256X:$src))),
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(VCVTTPS2DQZ256rr VR256X:$src)>;
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def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
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(VCVTTPS2DQZ256rm addr:$src)>;
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def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src))),
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(VCVTTPS2UDQZ256rr VR256X:$src)>;
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def : Pat<(v8i32 (fp_to_uint (loadv8f32 addr:$src))),
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(VCVTTPS2UDQZ256rm addr:$src)>;
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def : Pat<(v4i32 (fp_to_sint (v4f64 VR256X:$src))),
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(VCVTTPD2DQZ256rr VR256X:$src)>;
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def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
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(VCVTTPD2DQZ256rm addr:$src)>;
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def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src))),
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(VCVTTPD2UDQZ256rr VR256X:$src)>;
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def : Pat<(v4i32 (fp_to_uint (loadv4f64 addr:$src))),
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(VCVTTPD2UDQZ256rm addr:$src)>;
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// Special patterns to allow use of X86mcvtp2Int for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4i32 (X86cvtp2Int (v2f64 VR128X:$src))),
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@ -8343,28 +8291,6 @@ let Predicates = [HasVLX] in {
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(VCVTTPD2UDQZ128rmbkz VK2WM:$mask, addr:$src)>;
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}
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let Predicates = [HasDQI] in {
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def : Pat<(v8i64 (fp_to_sint (v8f32 VR256X:$src))),
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(VCVTTPS2QQZrr VR256X:$src)>;
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def : Pat<(v8i64 (fp_to_sint (loadv8f32 addr:$src))),
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(VCVTTPS2QQZrm addr:$src)>;
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def : Pat<(v8i64 (fp_to_uint (v8f32 VR256X:$src))),
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(VCVTTPS2UQQZrr VR256X:$src)>;
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def : Pat<(v8i64 (fp_to_uint (loadv8f32 addr:$src))),
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(VCVTTPS2UQQZrm addr:$src)>;
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def : Pat<(v8i64 (fp_to_sint (v8f64 VR512:$src))),
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(VCVTTPD2QQZrr VR512:$src)>;
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def : Pat<(v8i64 (fp_to_sint (loadv8f64 addr:$src))),
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(VCVTTPD2QQZrm addr:$src)>;
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def : Pat<(v8i64 (fp_to_uint (v8f64 VR512:$src))),
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(VCVTTPD2UQQZrr VR512:$src)>;
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def : Pat<(v8i64 (fp_to_uint (loadv8f64 addr:$src))),
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(VCVTTPD2UQQZrm addr:$src)>;
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}
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let Predicates = [HasDQI, HasVLX] in {
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def : Pat<(v2i64 (X86cvtp2Int (bc_v4f32 (v2f64 (X86vzload addr:$src))))),
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(VCVTPS2QQZ128rm addr:$src)>;
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@ -8409,50 +8335,20 @@ let Predicates = [HasDQI, HasVLX] in {
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(X86cvttp2ui (bc_v4f32 (v2f64 (X86vzload addr:$src)))),
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v2i64x_info.ImmAllZerosV)),
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(VCVTTPS2UQQZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src))),
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(VCVTTPS2QQZ256rr VR128X:$src)>;
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def : Pat<(v4i64 (fp_to_sint (loadv4f32 addr:$src))),
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(VCVTTPS2QQZ256rm addr:$src)>;
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def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src))),
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(VCVTTPS2UQQZ256rr VR128X:$src)>;
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def : Pat<(v4i64 (fp_to_uint (loadv4f32 addr:$src))),
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(VCVTTPS2UQQZ256rm addr:$src)>;
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def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src))),
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(VCVTTPD2QQZ128rr VR128X:$src)>;
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def : Pat<(v2i64 (fp_to_sint (loadv2f64 addr:$src))),
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(VCVTTPD2QQZ128rm addr:$src)>;
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def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src))),
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(VCVTTPD2UQQZ128rr VR128X:$src)>;
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def : Pat<(v2i64 (fp_to_uint (loadv2f64 addr:$src))),
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(VCVTTPD2UQQZ128rm addr:$src)>;
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def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src))),
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(VCVTTPD2QQZ256rr VR256X:$src)>;
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def : Pat<(v4i64 (fp_to_sint (loadv4f64 addr:$src))),
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(VCVTTPD2QQZ256rm addr:$src)>;
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def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src))),
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(VCVTTPD2UQQZ256rr VR256X:$src)>;
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def : Pat<(v4i64 (fp_to_uint (loadv4f64 addr:$src))),
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(VCVTTPD2UQQZ256rm addr:$src)>;
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}
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let Predicates = [HasAVX512, NoVLX] in {
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def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
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def : Pat<(v8i32 (X86cvttp2ui (v8f32 VR256X:$src1))),
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(EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
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(v16f32 (INSERT_SUBREG (IMPLICIT_DEF),
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VR256X:$src1, sub_ymm)))), sub_ymm)>;
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def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
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def : Pat<(v4i32 (X86cvttp2ui (v4f32 VR128X:$src1))),
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(EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
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(v16f32 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_xmm)>;
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def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src1))),
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def : Pat<(v4i32 (X86cvttp2ui (v4f64 VR256X:$src1))),
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(EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR256X:$src1, sub_ymm)))), sub_xmm)>;
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@ -8563,32 +8459,32 @@ let Predicates = [HasDQI, HasVLX] in {
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}
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let Predicates = [HasDQI, NoVLX] in {
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def : Pat<(v2i64 (fp_to_sint (v2f64 VR128X:$src1))),
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def : Pat<(v2i64 (X86cvttp2si (v2f64 VR128X:$src1))),
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(EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_xmm)>;
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def : Pat<(v4i64 (fp_to_sint (v4f32 VR128X:$src1))),
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def : Pat<(v4i64 (X86cvttp2si (v4f32 VR128X:$src1))),
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(EXTRACT_SUBREG (v8i64 (VCVTTPS2QQZrr
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(v8f32 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_ymm)>;
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def : Pat<(v4i64 (fp_to_sint (v4f64 VR256X:$src1))),
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def : Pat<(v4i64 (X86cvttp2si (v4f64 VR256X:$src1))),
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(EXTRACT_SUBREG (v8i64 (VCVTTPD2QQZrr
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR256X:$src1, sub_ymm)))), sub_ymm)>;
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def : Pat<(v2i64 (fp_to_uint (v2f64 VR128X:$src1))),
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def : Pat<(v2i64 (X86cvttp2ui (v2f64 VR128X:$src1))),
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(EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_xmm)>;
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def : Pat<(v4i64 (fp_to_uint (v4f32 VR128X:$src1))),
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def : Pat<(v4i64 (X86cvttp2ui (v4f32 VR128X:$src1))),
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(EXTRACT_SUBREG (v8i64 (VCVTTPS2UQQZrr
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(v8f32 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_ymm)>;
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def : Pat<(v4i64 (fp_to_uint (v4f64 VR256X:$src1))),
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def : Pat<(v4i64 (X86cvttp2ui (v4f64 VR256X:$src1))),
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(EXTRACT_SUBREG (v8i64 (VCVTTPD2UQQZrr
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR256X:$src1, sub_ymm)))), sub_ymm)>;
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@ -1480,17 +1480,6 @@ def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src)
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Sched<[WriteCvtPS2IYLd]>, VEX_WIG;
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}
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let Predicates = [HasAVX, NoVLX] in {
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def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
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(VCVTTPS2DQrr VR128:$src)>;
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def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
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(VCVTTPS2DQrm addr:$src)>;
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def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
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(VCVTTPS2DQYrr VR256:$src)>;
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def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
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(VCVTTPS2DQYrm addr:$src)>;
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}
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def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -1502,13 +1491,6 @@ def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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(v4i32 (X86cvttp2si (memopv4f32 addr:$src))))]>,
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Sched<[WriteCvtPS2ILd]>;
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let Predicates = [UseSSE2] in {
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def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
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(CVTTPS2DQrr VR128:$src)>;
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def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
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(CVTTPS2DQrm addr:$src)>;
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}
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// The assembler can recognize rr 256-bit instructions by seeing a ymm
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// register, but the same isn't true when using memory operands instead.
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// Provide other assembly rr and rm forms to address this explicitly.
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