forked from OSchip/llvm-project
[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64 types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This patch adds that support. As with lxvd2x/stxvd2x, this involves straightforward overriding of the patterns normally recognized for lvx/stvx, with preference given to the VSX patterns when VSX is enabled. In addition, the logic for permitting misaligned memory accesses is modified so that v4r32 and v4i32 are treated the same as v2f64 and v2i64 when VSX is enabled. Finally, the DAG generation for unaligned loads is changed to just use a normal LOAD (which will become lxvw4x) on P8 and later hardware, where unaligned loads are preferred over lvsl/lvx/lvx/vperm. A number of tests now generate the VSX loads/stores instead of lvx/stvx, so this patch adds VSX variants to those tests. I've also added <4 x float> tests to the vsx.ll test case, and created a vsx-p8.ll test case to be used for testing code generation for the P8Vector feature. For now, that simply tests the unaligned load/store behavior. This has been tested along with a temporary patch to enable the VSX and P8Vector features, with no new regressions encountered with or without the temporary patch applied. llvm-svn: 220047
This commit is contained in:
Bill Schmidt
parent
54468a5a58
commit
2d1128acb2
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@ -8312,6 +8312,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
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if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
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TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
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// P8 and later hardware should just use LOAD.
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!TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
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(VT == MVT::v16i8 || VT == MVT::v8i16 ||
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VT == MVT::v4i32 || VT == MVT::v4f32) &&
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LD->getAlignment() < ABIAlignment) {
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@ -9204,7 +9206,8 @@ bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
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if (VT.getSimpleVT().isVector()) {
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if (Subtarget.hasVSX()) {
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if (VT != MVT::v2f64 && VT != MVT::v2i64)
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if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
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VT != MVT::v4f32 && VT != MVT::v4i32)
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return false;
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} else {
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return false;
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@ -63,7 +63,8 @@ let Uses = [RM] in {
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def LXVW4X : XX1Form<31, 780,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvw4x $XT, $src", IIC_LdStLFD, []>;
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"lxvw4x $XT, $src", IIC_LdStLFD,
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[(set v4i32:$XT, (load xoaddr:$src))]>;
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}
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// Store indexed instructions
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@ -80,7 +81,8 @@ let Uses = [RM] in {
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def STXVW4X : XX1Form<31, 908,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvw4x $XT, $dst", IIC_LdStSTFD, []>;
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"stxvw4x $XT, $dst", IIC_LdStSTFD,
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[(store v4i32:$XT, xoaddr:$dst)]>;
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}
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// Add/Mul Instructions
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@ -811,6 +813,13 @@ def : Pat<(sext_inreg v2i64:$C, v2i32),
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def : Pat<(v2f64 (sint_to_fp (sext_inreg v2i64:$C, v2i32))),
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(XVCVSXWDP (XXSLDWI $C, $C, 1))>;
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// Loads.
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def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
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// Stores.
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def : Pat<(store v4i32:$rS, xoaddr:$dst),
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(STXVW4X $rS, xoaddr:$dst)>;
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} // AddedComplexity
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} // HasVSX
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mcpu=pwr7 | FileCheck %s
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; RUN: llc < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s
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; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -22,6 +23,9 @@ if.end210: ; preds = %entry
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; a multiple of 4).
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; CHECK: @copy_to_conceal
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; CHECK: stdx {{[0-9]+}}, 0,
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; CHECK-VSX: @copy_to_conceal
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; CHECK-VSX: stxvw4x {{[0-9]+}}, 0,
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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@ -92,10 +92,14 @@ entry:
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; CHECK-DAG: stdx
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; CHECK: stdx
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; For VSX on P7, unaligned loads and stores are preferable to aligned
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; stack slots, but lvsl/vperm is better still. (On P8 lxvw4x is preferable.)
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; Using unaligned stxvw4x is preferable on both machines.
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; CHECK-VSX: @foo6
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; CHECK-VSX-DAG: ld
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; CHECK-VSX-DAG: ld
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; CHECK-VSX-DAG: stdx
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; CHECK-VSX: stdx
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; CHECK-VSX-DAG: lvsl
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; CHECK-VSX-DAG: lvx
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; CHECK-VSX-DAG: lvx
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; CHECK-VSX: vperm
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; CHECK-VSX: stxvw4x
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}
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -16,6 +17,10 @@ entry:
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; CHECK-LABEL: @test1
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; CHECK: stvx 2,
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; CHECK: blr
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; CHECK-VSX-LABEL: @test1
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; CHECK-VSX: stxvw4x 34,
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; CHECK-VSX: blr
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}
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; Function Attrs: nounwind
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@ -35,6 +40,13 @@ entry:
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; CHECK: addi [[REGB:[0-9]+]], 1, 112
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; CHECK: lvx 2, [[REGB]], [[REG16]]
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; CHECK: blr
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; CHECK-VSX-LABEL: @test2
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; CHECK-VSX: ld {{[0-9]+}}, 112(1)
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; CHECK-VSX: li [[REG16:[0-9]+]], 16
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; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 112
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; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
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; CHECK-VSX: blr
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}
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; Function Attrs: nounwind
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@ -54,6 +66,13 @@ entry:
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; CHECK: addi [[REGB:[0-9]+]], 1, 128
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; CHECK: lvx 2, [[REGB]], [[REG16]]
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; CHECK: blr
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; CHECK-VSX-LABEL: @test3
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; CHECK-VSX: ld {{[0-9]+}}, 128(1)
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; CHECK-VSX: li [[REG16:[0-9]+]], 16
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; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 128
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; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
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; CHECK-VSX: blr
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}
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attributes #0 = { nounwind }
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
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@ -1,5 +1,7 @@
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; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false < %s | FileCheck -check-prefix=CHECK-VSX %s
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; This verifies that we generate correct spill/reload code for vector regs.
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@ -15,4 +17,9 @@ entry:
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; CHECK: stvx 2,
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; We would prefer to test for "stxvw4x 34," but current -O0 code
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; needlessly generates "vor 3,2,2 / stxvw4x 35,0,3", so we'll settle for
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; the opcode.
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; CHECK-VSX: stxvw4x
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declare void @foo(i32*)
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@ -0,0 +1,42 @@
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; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Unaligned loads/stores on P8 and later should use VSX where possible.
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define <2 x double> @test28u(<2 x double>* %a) {
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%v = load <2 x double>* %a, align 8
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ret <2 x double> %v
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; CHECK-LABEL: @test28u
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; CHECK: lxvd2x 34, 0, 3
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; CHECK: blr
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}
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define void @test29u(<2 x double>* %a, <2 x double> %b) {
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store <2 x double> %b, <2 x double>* %a, align 8
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ret void
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; CHECK-LABEL: @test29u
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; CHECK: stxvd2x 34, 0, 3
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; CHECK: blr
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}
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define <4 x float> @test32u(<4 x float>* %a) {
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%v = load <4 x float>* %a, align 8
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ret <4 x float> %v
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; CHECK-LABEL: @test32u
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; CHECK: lxvw4x 34, 0, 3
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; CHECK: blr
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}
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define void @test33u(<4 x float>* %a, <4 x float> %b) {
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store <4 x float> %b, <4 x float>* %a, align 8
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ret void
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; CHECK-LABEL: @test33u
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; CHECK: stxvw4x 34, 0, 3
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; CHECK: blr
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}
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@ -356,6 +356,63 @@ define void @test31(<2 x i64>* %a, <2 x i64> %b) {
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; CHECK: blr
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}
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define <4 x float> @test32(<4 x float>* %a) {
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%v = load <4 x float>* %a, align 16
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ret <4 x float> %v
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; CHECK-LABEL: @test32
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; CHECK: lxvw4x 34, 0, 3
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; CHECK: blr
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}
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define void @test33(<4 x float>* %a, <4 x float> %b) {
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store <4 x float> %b, <4 x float>* %a, align 16
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ret void
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; CHECK-LABEL: @test33
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; CHECK: stxvw4x 34, 0, 3
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; CHECK: blr
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}
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define <4 x float> @test32u(<4 x float>* %a) {
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%v = load <4 x float>* %a, align 8
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ret <4 x float> %v
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; CHECK-LABEL: @test32u
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; CHECK-DAG: lvsl
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; CHECK-DAG: lvx
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; CHECK-DAG: lvx
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; CHECK: vperm 2,
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; CHECK: blr
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}
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define void @test33u(<4 x float>* %a, <4 x float> %b) {
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store <4 x float> %b, <4 x float>* %a, align 8
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ret void
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; CHECK-LABEL: @test33u
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; CHECK: stxvw4x 34, 0, 3
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; CHECK: blr
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}
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define <4 x i32> @test34(<4 x i32>* %a) {
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%v = load <4 x i32>* %a, align 16
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ret <4 x i32> %v
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; CHECK-LABEL: @test34
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; CHECK: lxvw4x 34, 0, 3
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; CHECK: blr
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}
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define void @test35(<4 x i32>* %a, <4 x i32> %b) {
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store <4 x i32> %b, <4 x i32>* %a, align 16
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ret void
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; CHECK-LABEL: @test35
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; CHECK: stxvw4x 34, 0, 3
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; CHECK: blr
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}
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define <2 x double> @test40(<2 x i64> %a) {
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%v = uitofp <2 x i64> %a to <2 x double>
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ret <2 x double> %v
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