forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix selection of private stores
llvm-svn: 366249
This commit is contained in:
Matt Arsenault
parent
7161fb0be5
commit
2d10407719
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@ -1568,17 +1568,18 @@ defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, store_global>;
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multiclass MUBUFScratchStorePat <MUBUF_Pseudo InstrOffen,
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MUBUF_Pseudo InstrOffset,
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ValueType vt, PatFrag st> {
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ValueType vt, PatFrag st,
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RegisterClass rc = VGPR_32> {
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def : GCNPat <
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(st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
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i32:$soffset, u16imm:$offset)),
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(InstrOffen $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, 0)
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(InstrOffen rc:$value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, 0)
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>;
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def : GCNPat <
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(st vt:$value, (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset,
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u16imm:$offset)),
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(InstrOffset $value, $srsrc, $soffset, $offset, 0, 0, 0, 0)
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(InstrOffset rc:$value, $srsrc, $soffset, $offset, 0, 0, 0, 0)
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>;
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}
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@ -1587,9 +1588,9 @@ defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET
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defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i16, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, BUFFER_STORE_DWORD_OFFSET, i32, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, BUFFER_STORE_DWORDX2_OFFSET, v2i32, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX3_OFFEN, BUFFER_STORE_DWORDX3_OFFSET, v3i32, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, BUFFER_STORE_DWORDX4_OFFSET, v4i32, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, BUFFER_STORE_DWORDX2_OFFSET, v2i32, store_private, VReg_64>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX3_OFFEN, BUFFER_STORE_DWORDX3_OFFSET, v3i32, store_private, VReg_96>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, BUFFER_STORE_DWORDX4_OFFSET, v4i32, store_private, VReg_128>;
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let OtherPredicates = [D16PreservesUnusedBits] in {
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@ -0,0 +1,280 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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---
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name: store_private_s32_to_4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_private_s32_to_4
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: BUFFER_STORE_DWORD_OFFEN [[COPY]], [[COPY1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 5)
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; GFX9-LABEL: name: store_private_s32_to_4
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: BUFFER_STORE_DWORD_OFFEN [[COPY]], [[COPY1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 5)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(p5) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 5)
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...
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---
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name: store_private_s32_to_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_private_s32_to_2
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: BUFFER_STORE_SHORT_OFFEN [[COPY]], [[COPY1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 2, addrspace 5)
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; GFX9-LABEL: name: store_private_s32_to_2
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: BUFFER_STORE_SHORT_OFFEN [[COPY]], [[COPY1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 2, addrspace 5)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(p5) = COPY $vgpr1
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G_STORE %0, %1 :: (store 2, align 2, addrspace 5)
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...
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---
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name: store_private_s32_to_1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_private_s32_to_1
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: BUFFER_STORE_BYTE_OFFEN [[COPY]], [[COPY1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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; GFX9-LABEL: name: store_private_s32_to_1
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: BUFFER_STORE_BYTE_OFFEN [[COPY]], [[COPY1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(p5) = COPY $vgpr1
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G_STORE %0, %1 :: (store 1, align 1, addrspace 5)
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...
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---
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name: store_private_v2s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_private_v2s16
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY $vgpr1
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; GFX6: G_STORE [[COPY]](<2 x s16>), [[COPY1]](p5) :: (store 4, addrspace 5)
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; GFX9-LABEL: name: store_private_v2s16
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY $vgpr1
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; GFX9: G_STORE [[COPY]](<2 x s16>), [[COPY1]](p5) :: (store 4, addrspace 5)
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(p5) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 5)
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...
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---
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name: store_private_p3
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_private_p3
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY $vgpr1
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; GFX6: G_STORE [[COPY]](p3), [[COPY1]](p5) :: (store 4, addrspace 5)
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; GFX9-LABEL: name: store_private_p3
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY $vgpr1
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; GFX9: G_STORE [[COPY]](p3), [[COPY1]](p5) :: (store 4, addrspace 5)
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(p5) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 5)
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...
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---
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name: store_private_p5
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_private_p5
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY $vgpr1
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; GFX6: G_STORE [[COPY]](p5), [[COPY1]](p5) :: (store 4, addrspace 5)
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; GFX9-LABEL: name: store_private_p5
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY $vgpr1
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; GFX9: G_STORE [[COPY]](p5), [[COPY1]](p5) :: (store 4, addrspace 5)
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%0:vgpr(p5) = COPY $vgpr0
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%1:vgpr(p5) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 5)
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...
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---
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name: store_private_s32_to_1_fi_offset_4095
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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stack:
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- { id: 0, size: 4096, alignment: 4 }
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body: |
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bb.0:
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; GFX6-LABEL: name: store_private_s32_to_1_fi_offset_4095
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; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
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; GFX6: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, implicit $exec
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; GFX6: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX6: BUFFER_STORE_BYTE_OFFEN [[V_MOV_B32_e32_2]], %2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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; GFX9-LABEL: name: store_private_s32_to_1_fi_offset_4095
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; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX9: BUFFER_STORE_BYTE_OFFEN [[V_MOV_B32_e32_]], %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4095, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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%0:vgpr(p5) = G_FRAME_INDEX %stack.0
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%1:vgpr(s32) = G_CONSTANT i32 4095
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%2:vgpr(p5) = G_GEP %0, %1
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%3:vgpr(s32) = G_CONSTANT i32 0
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G_STORE %3, %2 :: (store 1, align 1, addrspace 5)
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...
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---
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name: store_private_s32_to_1_constant_4095
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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stack:
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- { id: 0, size: 4096, alignment: 4 }
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body: |
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bb.0:
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; GFX6-LABEL: name: store_private_s32_to_1_constant_4095
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; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX6: BUFFER_STORE_BYTE_OFFSET [[V_MOV_B32_e32_]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4095, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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; GFX9-LABEL: name: store_private_s32_to_1_constant_4095
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; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX9: BUFFER_STORE_BYTE_OFFSET [[V_MOV_B32_e32_]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4095, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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%0:vgpr(p5) = G_CONSTANT i32 4095
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%1:vgpr(s32) = G_CONSTANT i32 0
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G_STORE %1, %0 :: (store 1, align 1, addrspace 5)
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...
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---
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name: store_private_s32_to_1_constant_4096
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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stack:
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- { id: 0, size: 4096, alignment: 4 }
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body: |
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bb.0:
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; GFX6-LABEL: name: store_private_s32_to_1_constant_4096
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; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
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; GFX6: BUFFER_STORE_BYTE_OFFEN [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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; GFX9-LABEL: name: store_private_s32_to_1_constant_4096
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; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
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; GFX9: BUFFER_STORE_BYTE_OFFEN [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (store 1, addrspace 5)
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%0:vgpr(p5) = G_CONSTANT i32 4096
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%1:vgpr(s32) = G_CONSTANT i32 0
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G_STORE %1, %0 :: (store 1, align 1, addrspace 5)
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...
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