forked from OSchip/llvm-project
[llvm-readobj][ELF] Teach llvm-readobj to show arch specific ELF section's flags
Some architecture specific ELF section flags might have the same value (for example SHF_X86_64_LARGE and SHF_HEX_GPREL) and we have to check machine architectures to select an appropriate set of possible flags. The patch selects architecture specific flags into separate arrays `ElfxxxSectionFlags` and combines `ElfSectionFlags` and `ElfxxxSectionFlags` before pass to the `StreamWriter::printFlags()` method. Differential Revision: http://reviews.llvm.org/D16269 llvm-svn: 258334
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@ -336,6 +336,9 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
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BCase(EF_AVR_ARCH_XMEGA6)
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BCase(EF_AVR_ARCH_XMEGA7)
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break;
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case ELF::EM_AMDGPU:
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case ELF::EM_X86_64:
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break;
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default:
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llvm_unreachable("Unsupported architecture");
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}
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@ -422,6 +425,22 @@ void ScalarBitSetTraits<ELFYAML::ELF_SHF>::bitset(IO &IO,
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BCase(SHF_AMDGPU_HSA_CODE)
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BCase(SHF_AMDGPU_HSA_AGENT)
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break;
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case ELF::EM_HEXAGON:
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BCase(SHF_HEX_GPREL)
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break;
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case ELF::EM_MIPS:
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BCase(SHF_MIPS_NODUPES)
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BCase(SHF_MIPS_NAMES)
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BCase(SHF_MIPS_LOCAL)
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BCase(SHF_MIPS_NOSTRIP)
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BCase(SHF_MIPS_GPREL)
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BCase(SHF_MIPS_MERGE)
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BCase(SHF_MIPS_ADDR)
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BCase(SHF_MIPS_STRING)
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break;
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case ELF::EM_X86_64:
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BCase(SHF_X86_64_LARGE)
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break;
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default:
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// Nothing to do.
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break;
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@ -327,7 +327,7 @@ ELF-MIPS64EL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ]
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ELF-MIPS64EL-NEXT: AddressAlign: 0x0000000000000010
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ELF-MIPS64EL-NEXT: - Name: .MIPS.options
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ELF-MIPS64EL-NEXT: Type: SHT_MIPS_OPTIONS
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ELF-MIPS64EL-NEXT: Flags: [ SHF_ALLOC ]
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ELF-MIPS64EL-NEXT: Flags: [ SHF_ALLOC, SHF_MIPS_NOSTRIP ]
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ELF-MIPS64EL-NEXT: AddressAlign: 0x0000000000000008
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ELF-MIPS64EL-NEXT: Content: '01280000000000000000000000000000000000000000000000000000000000000000000000000000'
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ELF-MIPS64EL-NEXT: - Name: .pdr
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@ -0,0 +1,90 @@
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# Check that llvm-readobj shows arch specific ELF section flags.
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# RUN: yaml2obj -format=elf -docnum 1 %s > %t-amdgpu.o
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# RUN: llvm-readobj -s %t-amdgpu.o | FileCheck -check-prefix=AMD %s
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# AMD: Flags [ (0x300000)
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# AMD-NEXT: SHF_AMDGPU_HSA_GLOBAL (0x100000)
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# AMD-NEXT: SHF_AMDGPU_HSA_READONLY (0x200000)
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# AMD-NEXT: ]
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# amdgpu.o
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---
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FileHeader:
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Class: ELFCLASS64
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Data: ELFDATA2LSB
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OSABI: ELFOSABI_GNU
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Type: ET_REL
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Machine: EM_AMDGPU
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Flags: []
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Sections:
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- Name: .amdgpu
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Type: SHT_PROGBITS
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Flags: [SHF_AMDGPU_HSA_GLOBAL, SHF_AMDGPU_HSA_READONLY]
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Size: 4
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# RUN: yaml2obj -format=elf -docnum 2 %s > %t-hex.o
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# RUN: llvm-readobj -s %t-hex.o | FileCheck -check-prefix=HEX %s
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# HEX: Flags [ (0x10000000)
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# HEX-NEXT: SHF_HEX_GPREL (0x10000000)
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# HEX-NEXT: ]
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# hex.o
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---
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FileHeader:
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Class: ELFCLASS32
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Data: ELFDATA2LSB
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Type: ET_REL
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Machine: EM_HEXAGON
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Flags: []
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Sections:
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- Name: .hex
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Type: SHT_PROGBITS
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Flags: [SHF_HEX_GPREL]
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Size: 4
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# RUN: yaml2obj -format=elf -docnum 3 %s > %t-mips.o
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# RUN: llvm-readobj -s %t-mips.o | FileCheck -check-prefix=MIPS %s
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# MIPS: Flags [ (0x38000000)
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# MIPS-NEXT: SHF_MIPS_GPREL (0x10000000)
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# MIPS-NEXT: SHF_MIPS_MERGE (0x20000000)
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# MIPS-NEXT: SHF_MIPS_NOSTRIP (0x8000000)
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# MIPS-NEXT: ]
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# mips.o
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---
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FileHeader:
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Class: ELFCLASS32
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Data: ELFDATA2LSB
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Type: ET_REL
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Machine: EM_MIPS
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Flags: []
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Sections:
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- Name: .mips
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Type: SHT_PROGBITS
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Flags: [SHF_MIPS_GPREL, SHF_MIPS_MERGE, SHF_MIPS_NOSTRIP]
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Size: 4
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# RUN: yaml2obj -format=elf -docnum 4 %s > %t-x86_64.o
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# RUN: llvm-readobj -s %t-x86_64.o | FileCheck -check-prefix=X86_64 %s
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# X86_64: Flags [ (0x10000000)
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# X86_64-NEXT: SHF_X86_64_LARGE (0x10000000)
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# X86_64-NEXT: ]
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# x86_64.o
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---
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FileHeader:
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Class: ELFCLASS64
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Data: ELFDATA2LSB
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Type: ET_REL
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Machine: EM_X86_64
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Flags: []
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Sections:
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- Name: .x86_64
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Type: SHT_PROGBITS
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Flags: [SHF_X86_64_LARGE]
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Size: 4
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...
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@ -806,13 +806,34 @@ static const EnumEntry<unsigned> ElfSectionFlags[] = {
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_TLS ),
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LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_CP_SECTION),
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LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_DP_SECTION),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NOSTRIP ),
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};
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static const EnumEntry<unsigned> ElfAMDGPUSectionFlags[] = {
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_GLOBAL),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_READONLY),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_CODE),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_AGENT)
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};
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static const EnumEntry<unsigned> ElfHexagonSectionFlags[] = {
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_HEX_GPREL)
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};
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static const EnumEntry<unsigned> ElfMipsSectionFlags[] = {
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NODUPES),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NAMES ),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_LOCAL ),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NOSTRIP),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_GPREL ),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_MERGE ),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_ADDR ),
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_STRING )
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};
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static const EnumEntry<unsigned> ElfX86_64SectionFlags[] = {
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LLVM_READOBJ_ENUM_ENT(ELF, SHF_X86_64_LARGE)
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};
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static const char *getElfSegmentType(unsigned Arch, unsigned Type) {
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// Check potentially overlapped processor-specific
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// program header type.
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@ -1118,7 +1139,31 @@ void ELFDumper<ELFT>::printSections() {
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W.printHex("Type",
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getElfSectionType(Obj->getHeader()->e_machine, Sec.sh_type),
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Sec.sh_type);
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W.printFlags("Flags", Sec.sh_flags, makeArrayRef(ElfSectionFlags));
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std::vector<EnumEntry<unsigned>> SectionFlags(std::begin(ElfSectionFlags),
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std::end(ElfSectionFlags));
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switch (Obj->getHeader()->e_machine) {
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case EM_AMDGPU:
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SectionFlags.insert(SectionFlags.end(), std::begin(ElfAMDGPUSectionFlags),
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std::end(ElfAMDGPUSectionFlags));
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break;
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case EM_HEXAGON:
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SectionFlags.insert(SectionFlags.end(),
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std::begin(ElfHexagonSectionFlags),
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std::end(ElfHexagonSectionFlags));
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break;
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case EM_MIPS:
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SectionFlags.insert(SectionFlags.end(), std::begin(ElfMipsSectionFlags),
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std::end(ElfMipsSectionFlags));
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break;
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case EM_X86_64:
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SectionFlags.insert(SectionFlags.end(), std::begin(ElfX86_64SectionFlags),
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std::end(ElfX86_64SectionFlags));
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break;
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default:
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// Nothing to do.
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break;
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}
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W.printFlags("Flags", Sec.sh_flags, makeArrayRef(SectionFlags));
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W.printHex("Address", Sec.sh_addr);
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W.printHex("Offset", Sec.sh_offset);
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W.printNumber("Size", Sec.sh_size);
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