diff --git a/llvm/include/llvm/ADT/PriorityWorklist.h b/llvm/include/llvm/ADT/PriorityWorklist.h index f8a3aac7b539..9dd575fa96bf 100644 --- a/llvm/include/llvm/ADT/PriorityWorklist.h +++ b/llvm/include/llvm/ADT/PriorityWorklist.h @@ -17,6 +17,7 @@ #define LLVM_ADT_PRIORITYWORKLIST_H #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include #include diff --git a/llvm/include/llvm/ADT/SetVector.h b/llvm/include/llvm/ADT/SetVector.h index 0e31a6567ea0..01d38a8f3b97 100644 --- a/llvm/include/llvm/ADT/SetVector.h +++ b/llvm/include/llvm/ADT/SetVector.h @@ -186,7 +186,7 @@ public: template bool remove_if(UnaryPredicate P) { typename vector_type::iterator I = - remove_if(vector_, TestAndEraseFromSet(P, set_)); + llvm::remove_if(vector_, TestAndEraseFromSet(P, set_)); if (I == vector_.end()) return false; vector_.erase(I, vector_.end()); diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 4ae31627f78b..cb0388def5e8 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -1434,7 +1434,7 @@ MemoryDepChecker::getInstructionsForAccess(Value *Ptr, bool isWrite) const { auto &IndexVector = Accesses.find(Access)->second; SmallVector Insts; - std::transform(IndexVector.begin(), IndexVector.end(), + transform(IndexVector, std::back_inserter(Insts), [&](unsigned Idx) { return this->InstMap[Idx]; }); return Insts; @@ -1823,9 +1823,8 @@ static SmallVector, 4> expandBounds( // Here we're relying on the SCEV Expander's cache to only emit code for the // same bounds once. - std::transform( - PointerChecks.begin(), PointerChecks.end(), - std::back_inserter(ChecksWithBounds), + transform( + PointerChecks, std::back_inserter(ChecksWithBounds), [&](const RuntimePointerChecking::PointerCheck &Check) { PointerBounds First = expandBounds(Check.first, L, Loc, Exp, SE, PtrRtChecking), diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 2c3292527f52..9bb8b2f50bb3 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -2858,7 +2858,7 @@ std::error_code BitcodeReader::resolveGlobalAndIndirectSymbolInits() { static APInt readWideAPInt(ArrayRef Vals, unsigned TypeBits) { SmallVector Words(Vals.size()); - std::transform(Vals.begin(), Vals.end(), Words.begin(), + transform(Vals, Words.begin(), BitcodeReader::decodeSignRotatedValue); return APInt(TypeBits, Words); diff --git a/llvm/lib/IR/LLVMContextImpl.h b/llvm/lib/IR/LLVMContextImpl.h index e808a60aa1b5..1d0b1b1524ae 100644 --- a/llvm/lib/IR/LLVMContextImpl.h +++ b/llvm/lib/IR/LLVMContextImpl.h @@ -998,7 +998,8 @@ public: /// /// Erases all attachments matching the \c shouldRemove predicate. template void remove_if(PredTy shouldRemove) { - Attachments.erase(remove_if(Attachments, shouldRemove), Attachments.end()); + Attachments.erase(llvm::remove_if(Attachments, shouldRemove), + Attachments.end()); } }; diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 8d649250f656..383b7ca4ddd0 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1266,7 +1266,7 @@ void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, SmallVector Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); @@ -1305,7 +1305,7 @@ void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, SmallVector Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); @@ -1360,7 +1360,7 @@ void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, SmallVector Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); @@ -1390,7 +1390,7 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, SmallVector Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); diff --git a/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp b/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp index 9e3d7e181bb9..358253266eb6 100644 --- a/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp +++ b/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp @@ -347,7 +347,7 @@ public: // Collect the pointers of the candidate loads. // FIXME: SmallSet does not work with std::inserter. std::set CandLoadPtrs; - std::transform(Candidates.begin(), Candidates.end(), + transform(Candidates, std::inserter(CandLoadPtrs, CandLoadPtrs.begin()), std::mem_fn(&StoreToLoadForwardingCandidate::getLoadPtr));