forked from OSchip/llvm-project
Add stubs of incomplete watchpoint implementation with "FIXME" markers.
llvm-svn: 138790
This commit is contained in:
parent
154a2fd3cb
commit
2cf3222029
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@ -625,6 +625,117 @@ DNBArchImplI386::NotifyException(MachException::Data& exc)
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return false;
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}
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#ifndef DR_FIRSTADDR
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#define DR_FIRSTADDR 0
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#endif
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#ifndef DR_LASTADDR
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#define DR_LASTADDR 3
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#endif
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#ifndef DR_STATUS
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#define DR_STATUS 6
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#endif
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#ifndef DR_CONTROL
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#define DR_CONTROL 7
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#endif
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uint32_t
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DNBArchImplI386::NumSupportedHardwareWatchpoints()
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{
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return DR_LASTADDR - DR_FIRSTADDR + 1;
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}
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uint32_t
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DNBArchImplI386::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write)
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{
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write);
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const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
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// Can't watch zero bytes
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if (size == 0)
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return INVALID_NUB_HW_INDEX;
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// We must watch for either read or write
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if (read == false && write == false)
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return INVALID_NUB_HW_INDEX;
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//
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// FIXME: Add implmentation.
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//
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// Read the debug state
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kern_return_t kret = GetDBGState(false);
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if (kret == KERN_SUCCESS)
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{
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// Check to make sure we have the needed hardware support
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uint32_t i = 0;
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DBG debug_state = m_state.context.dbg;
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for (i=0; i<num_hw_watchpoints; ++i)
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{
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uint64_t dr_val = 0;
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switch (i) {
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case 0:
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dr_val = debug_state.__dr0; break;
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case 1:
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dr_val = debug_state.__dr1; break;
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case 2:
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dr_val = debug_state.__dr2; break;
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case 3:
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dr_val = debug_state.__dr3; break;
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default:
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break;
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}
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if (dr_val != 0)
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break; // We found an available hw breakpoint slot (in i)
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}
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// See if we found an available hw breakpoint slot above
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if (i < num_hw_watchpoints)
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{
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kret = SetDBGState();
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImpI386::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret);
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if (kret == KERN_SUCCESS)
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return i;
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}
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else
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{
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImpl386::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
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}
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}
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return INVALID_NUB_HW_INDEX;
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}
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bool
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DNBArchImplI386::DisableHardwareWatchpoint (uint32_t hw_index)
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{
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kern_return_t kret = GetDBGState(false);
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const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
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if (kret == KERN_SUCCESS)
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{
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if (hw_index < num_hw_points)
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{
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//
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// FIXEME: Add implementation.
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//
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::DisableHardwareWatchpoint( %u )",
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hw_index);
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kret = SetDBGState();
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if (kret == KERN_SUCCESS)
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return true;
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}
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}
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return false;
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}
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// Set the single step bit in the processor status register.
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kern_return_t
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@ -51,6 +51,10 @@ public:
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virtual bool ThreadDidStop();
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virtual bool NotifyException(MachException::Data& exc);
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virtual uint32_t NumSupportedHardwareWatchpoints();
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virtual uint32_t EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write);
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virtual bool DisableHardwareWatchpoint (uint32_t hw_break_index);
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protected:
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kern_return_t EnableHardwareSingleStep (bool enable);
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@ -554,6 +554,117 @@ DNBArchImplX86_64::NotifyException(MachException::Data& exc)
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return false;
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}
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#ifndef DR_FIRSTADDR
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#define DR_FIRSTADDR 0
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#endif
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#ifndef DR_LASTADDR
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#define DR_LASTADDR 3
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#endif
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#ifndef DR_STATUS
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#define DR_STATUS 6
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#endif
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#ifndef DR_CONTROL
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#define DR_CONTROL 7
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#endif
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uint32_t
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DNBArchImplX86_64::NumSupportedHardwareWatchpoints()
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{
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return DR_LASTADDR - DR_FIRSTADDR + 1;
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}
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uint32_t
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DNBArchImplX86_64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write)
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{
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write);
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const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
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// Can't watch zero bytes
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if (size == 0)
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return INVALID_NUB_HW_INDEX;
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// We must watch for either read or write
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if (read == false && write == false)
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return INVALID_NUB_HW_INDEX;
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//
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// FIXME: Add implmentation.
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//
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// Read the debug state
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kern_return_t kret = GetDBGState(false);
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if (kret == KERN_SUCCESS)
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{
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// Check to make sure we have the needed hardware support
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uint32_t i = 0;
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DBG debug_state = m_state.context.dbg;
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for (i=0; i<num_hw_watchpoints; ++i)
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{
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uint64_t dr_val = 0;
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switch (i) {
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case 0:
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dr_val = debug_state.__dr0; break;
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case 1:
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dr_val = debug_state.__dr1; break;
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case 2:
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dr_val = debug_state.__dr2; break;
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case 3:
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dr_val = debug_state.__dr3; break;
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default:
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break;
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}
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if (dr_val != 0)
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break; // We found an available hw breakpoint slot (in i)
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}
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// See if we found an available hw breakpoint slot above
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if (i < num_hw_watchpoints)
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{
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kret = SetDBGState();
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret);
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if (kret == KERN_SUCCESS)
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return i;
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}
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else
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{
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
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}
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}
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return INVALID_NUB_HW_INDEX;
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}
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bool
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DNBArchImplX86_64::DisableHardwareWatchpoint (uint32_t hw_index)
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{
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kern_return_t kret = GetDBGState(false);
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const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
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if (kret == KERN_SUCCESS)
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{
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if (hw_index < num_hw_points)
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{
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//
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// FIXEME: Add implementation.
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//
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DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::DisableHardwareWatchpoint( %u )",
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hw_index);
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kret = SetDBGState();
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if (kret == KERN_SUCCESS)
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return true;
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}
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}
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return false;
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}
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// Set the single step bit in the processor status register.
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kern_return_t
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@ -50,6 +50,10 @@ public:
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virtual bool ThreadDidStop();
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virtual bool NotifyException(MachException::Data& exc);
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virtual uint32_t NumSupportedHardwareWatchpoints();
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virtual uint32_t EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write);
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virtual bool DisableHardwareWatchpoint (uint32_t hw_break_index);
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protected:
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kern_return_t EnableHardwareSingleStep (bool enable);
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@ -147,12 +147,12 @@ RNBRemote::CreatePacketTable ()
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// t.push_back (Packet (write_data_to_memory, &RNBRemote::HandlePacket_X, NULL, "X", "Write data to memory"));
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// t.push_back (Packet (insert_hardware_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "Z1", "Insert hardware breakpoint"));
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// t.push_back (Packet (remove_hardware_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "z1", "Remove hardware breakpoint"));
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// t.push_back (Packet (insert_write_watch_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "Z2", "Insert write watchpoint"));
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// t.push_back (Packet (remove_write_watch_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "z2", "Remove write watchpoint"));
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// t.push_back (Packet (insert_read_watch_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "Z3", "Insert read watchpoint"));
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// t.push_back (Packet (remove_read_watch_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "z3", "Remove read watchpoint"));
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// t.push_back (Packet (insert_access_watch_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "Z4", "Insert access watchpoint"));
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// t.push_back (Packet (remove_access_watch_bp, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "z4", "Remove access watchpoint"));
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t.push_back (Packet (insert_write_watch_bp, &RNBRemote::HandlePacket_z, NULL, "Z2", "Insert write watchpoint"));
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t.push_back (Packet (remove_write_watch_bp, &RNBRemote::HandlePacket_z, NULL, "z2", "Remove write watchpoint"));
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t.push_back (Packet (insert_read_watch_bp, &RNBRemote::HandlePacket_z, NULL, "Z3", "Insert read watchpoint"));
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t.push_back (Packet (remove_read_watch_bp, &RNBRemote::HandlePacket_z, NULL, "z3", "Remove read watchpoint"));
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t.push_back (Packet (insert_access_watch_bp, &RNBRemote::HandlePacket_z, NULL, "Z4", "Insert access watchpoint"));
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t.push_back (Packet (remove_access_watch_bp, &RNBRemote::HandlePacket_z, NULL, "z4", "Remove access watchpoint"));
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t.push_back (Packet (query_current_thread_id, &RNBRemote::HandlePacket_qC, NULL, "qC", "Query current thread ID"));
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t.push_back (Packet (query_get_pid, &RNBRemote::HandlePacket_qGetPid, NULL, "qGetPid", "Query process id"));
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// t.push_back (Packet (query_memory_crc, &RNBRemote::HandlePacket_UNIMPLEMENTED, NULL, "qCRC:", "Compute CRC of memory region"));
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