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ARMEB: Fix trunc store for vector types 

Reviewed at http://reviews.llvm.org/D4135

llvm-svn: 211010
This commit is contained in:
Christian Pirker 2014-06-16 09:17:30 +00:00
parent 739f4302b5
commit 2cc1cf0d4b
2 changed files with 28 additions and 1 deletions
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3
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -8464,7 +8464,8 @@ static SDValue PerformSTORECombine(SDNode *N,
SDLoc DL(St);
SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
for (unsigned i = 0; i < NumElems; ++i)
ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
// Can't shuffle using an illegal type.
if (!TLI.isTypeLegal(WideVecVT)) return SDValue();

26
llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll Normal file
View File

@ -0,0 +1,26 @@
; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %storeaddr ) {
; CHECK-LABEL: vector_trunc_store_2i64_to_2i16:
; CHECK: vmovn.i64 [[REG:d[0-9]+]]
; CHECK: vrev32.16 [[REG]], [[REG]]
; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
; CHECK: vrev32.16 [[REG]], [[REG2]]
%1 = load <2 x i64>* %loadaddr
%2 = trunc <2 x i64> %1 to <2 x i16>
store <2 x i16> %2, <2 x i16>* %storeaddr
ret void
}
define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %storeaddr ) {
; CHECK-LABEL: vector_trunc_store_4i32_to_4i8:
; CHECK: vmovn.i32 [[REG:d[0-9]+]]
; CHECK: vrev16.8 [[REG]], [[REG]]
; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
; CHECK: vrev32.8 [[REG]], [[REG2]]
%1 = load <4 x i32>* %loadaddr
%2 = trunc <4 x i32> %1 to <4 x i8>
store <4 x i8> %2, <4 x i8>* %storeaddr
ret void
}