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[X86] Add relaxtion logic for ADC instructions. 

Prior to this patch, we would wrongly stick to the variant with imm8 encoding
even when the relocation could not fit that size.

rdar://problem/23785506

llvm-svn: 255570
This commit is contained in:
Quentin Colombet 2015-12-14 23:12:40 +00:00
parent 6a5def90d9
commit 2cb8a51c1f
2 changed files with 24 additions and 0 deletions
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8
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
View File

@ -204,6 +204,14 @@ static unsigned getRelaxedOpcodeArith(unsigned Op) {
case X86::ADD64ri8: return X86::ADD64ri32;
case X86::ADD64mi8: return X86::ADD64mi32;
// ADC
case X86::ADC16ri8: return X86::ADC16ri;
case X86::ADC16mi8: return X86::ADC16mi;
case X86::ADC32ri8: return X86::ADC32ri;
case X86::ADC32mi8: return X86::ADC32mi;
case X86::ADC64ri8: return X86::ADC64ri32;
case X86::ADC64mi8: return X86::ADC64mi32;
// SUB
case X86::SUB16ri8: return X86::SUB16ri;
case X86::SUB16mi8: return X86::SUB16mi;

16
llvm/test/MC/ELF/relax-arith.s
View File

@ -123,3 +123,19 @@ bar:
.section push,"x"
pushw $foo
push $foo
// CHECK: Disassembly of section adc:
// CHECK-NEXT: adc:
// CHECK-NEXT: 0: 66 81 d3 00 00 adcw $0, %bx
// CHECK-NEXT: 5: 66 81 14 25 00 00 00 00 00 00 adcw $0, 0
// CHECK-NEXT: f: 81 d3 00 00 00 00 adcl $0, %ebx
// CHECK-NEXT: 15: 81 14 25 00 00 00 00 00 00 00 00 adcl $0, 0
// CHECK-NEXT: 20: 48 81 d3 00 00 00 00 adcq $0, %rbx
// CHECK-NEXT: 27: 48 81 14 25 00 00 00 00 00 00 00 00 adcq $0, 0
.section adc,"x"
adc $foo, %bx
adcw $foo, bar
adc $foo, %ebx
adcl $foo, bar
adc $foo, %rbx
adcq $foo, bar