forked from OSchip/llvm-project
[mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions
Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
This commit is contained in:
Hrvoje Varga
parent
dbea1a1e51
commit
2cb74ac3c3
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@ -918,6 +918,17 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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Size = 4;
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return Result;
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}
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if (hasMips32r6()) {
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DEBUG(dbgs() << "Trying MicroMips32r6FPU table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableMicroMips32r6FPU32, Instr, Insn,
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Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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}
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// This is an invalid instruction. Let the disassembler move forward by the
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// minimum instruction size.
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Size = 2;
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@ -870,3 +870,49 @@ class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rt;
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bits<5> rs;
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bits<3> sel;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-14} = 0;
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let Inst{13-11} = sel;
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let Inst{10-6} = funct;
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let Inst{5-0} = opcode;
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}
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class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
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: MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = rt;
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let Inst{20-16} = fs;
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let Inst{15-14} = 0;
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let Inst{13-6} = funct;
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let Inst{5-0} = 0b111011;
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}
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class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rt;
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bits<5> impl;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = impl;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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@ -71,6 +71,12 @@ class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
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class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
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class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
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class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
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class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
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class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
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class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
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class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
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class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>;
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class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
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class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
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class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
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class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
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@ -538,6 +544,62 @@ class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
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class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
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class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
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class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
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RegisterOperand SrcRC> {
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dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
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dag OutOperandList = (outs DstRC:$rs);
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string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
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list<dag> Pattern = [];
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Format f = FrmFR;
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string BaseOpcode = opstr;
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}
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class MTC1_MMR6_DESC_BASE<
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string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
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: MipsR6Inst {
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dag InOperandList = (ins SrcRC:$rt);
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dag OutOperandList = (outs DstRC:$fs);
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string AsmString = !strconcat(opstr, "\t$rt, $fs");
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list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
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Format f = FrmFR;
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InstrItinClass Itinerary = Itin;
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string BaseOpcode = opstr;
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}
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class MTC1_64_MMR6_DESC_BASE<
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string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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InstrItinClass Itin = NoItinerary> : MipsR6Inst {
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dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
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dag OutOperandList = (outs DstRC:$fs);
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string AsmString = !strconcat(opstr, "\t$rt, $fs");
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list<dag> Pattern = [];
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Format f = FrmFR;
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InstrItinClass Itinerary = Itin;
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string BaseOpcode = opstr;
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// $fs_in is part of a white lie to work around a widespread bug in the FPU
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// implementation. See expandBuildPairF64 for details.
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let Constraints = "$fs = $fs_in";
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}
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class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
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RegisterOperand SrcRC> {
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dag InOperandList = (ins SrcRC:$rt);
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dag OutOperandList = (outs DstRC:$impl);
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string AsmString = !strconcat(opstr, "\t$rt, $impl");
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list<dag> Pattern = [];
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Format f = FrmFR;
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string BaseOpcode = opstr;
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}
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class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>;
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class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
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II_MTC1, bitconvert>, HARDFLOAT;
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class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd>;
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class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>;
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class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd>,
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HARDFLOAT, FGR_32;
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class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, GPR32Opnd>,
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HARDFLOAT, FGR_64;
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class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>;
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/// Floating Point Instructions
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class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
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InstrItinClass Itin, bit isComm,
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@ -999,6 +1061,16 @@ def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
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def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
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def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
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def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
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def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
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def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
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def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
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def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
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def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
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let DecoderNamespace = "MicroMips32r6FPU" in {
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def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
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ISA_MICROMIPS32R6;
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}
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def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
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def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
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def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
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def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
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@ -1238,6 +1310,12 @@ def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"rdhwr $rt, $rs",
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(RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"mtc0 $rt, $rs",
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(MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"mthc0 $rt, $rs",
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(MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
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ISA_MICROMIPS32R6;
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//===----------------------------------------------------------------------===//
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//
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@ -84,3 +84,20 @@ class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
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let Inst{10-9} = 0b00;
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let Inst{8-0} = funct;
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}
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class POOL32S_DMFTC0_FM_MMR6<string instr_asm, bits<5> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rt;
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bits<5> rs;
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bits<3> sel;
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bits<32> Inst;
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let Inst{31-26} = 0b010110;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-14} = 0;
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let Inst{13-11} = sel;
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let Inst{10-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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@ -31,6 +31,9 @@ class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
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class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
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class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
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class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
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class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
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class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
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class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
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//===----------------------------------------------------------------------===//
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//
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@ -98,6 +101,10 @@ class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
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class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
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class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
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MipsIns>;
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class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>;
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class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
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II_DMTC1, bitconvert>;
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class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>;
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//===----------------------------------------------------------------------===//
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//
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@ -131,4 +138,16 @@ let DecoderNamespace = "MicroMipsR6" in {
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ISA_MICROMIPS64R6;
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def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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}
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : MipsInstAlias<"dmtc0 $rt, $rd",
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(DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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@ -116,8 +116,6 @@ def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
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II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
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def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
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MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
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def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
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def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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MADDS_FM_MM<0x1>;
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@ -147,4 +145,6 @@ let AdditionalPredicates = [InMicroMips] in {
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ROUND_W_FM_MM<0, 0x6c>;
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def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
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fsqrt>, ROUND_W_FM_MM<0, 0x28>;
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def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
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}
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@ -625,7 +625,10 @@ def : MipsInstAlias<"dsrl $rd, $rt, $rs",
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// Two operand (implicit 0 selector) versions:
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def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"dmtc0 $rt, $rd",
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(DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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}
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def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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@ -373,16 +373,20 @@ def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
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MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
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let DecoderNamespace = "Mips64";
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}
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def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
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def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
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let DecoderNamespace = "Mips64";
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let AdditionalPredicates = [NotInMicroMips] in {
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def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
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def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
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let DecoderNamespace = "Mips64";
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}
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}
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def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
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bitconvert>, MFC1_FM<1>, ISA_MIPS3;
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def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
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bitconvert>, MFC1_FM<5>, ISA_MIPS3;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
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bitconvert>, MFC1_FM<5>, ISA_MIPS3;
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}
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def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
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ABSS_FM<0x6, 16>;
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|
@ -1888,7 +1888,10 @@ def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, MipsIns>,
|
|||
|
||||
/// Move Control Registers From/To CPU Registers
|
||||
def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
|
||||
def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>,
|
||||
ISA_MIPS32;
|
||||
}
|
||||
def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
|
||||
def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
|
||||
|
||||
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|
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|||
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|
@ -258,3 +258,13 @@
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|||
0x00 0x0f 0x47 0x7c # CHECK: di $15
|
||||
0x00 0x00 0x43 0x7c # CHECK: tlbinv
|
||||
0x00 0x00 0x53 0x7c # CHECK: tlbinvf
|
||||
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
|
||||
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
|
||||
0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7
|
||||
0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4
|
||||
0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6
|
||||
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0
|
||||
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8
|
||||
0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
|
||||
0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
|
||||
0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
|
||||
|
|
|
|||
|
|
@ -174,3 +174,18 @@
|
|||
0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5
|
||||
0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5
|
||||
0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5
|
||||
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
|
||||
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
|
||||
0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7
|
||||
0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4
|
||||
0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6
|
||||
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0
|
||||
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8
|
||||
0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
|
||||
0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
|
||||
0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
|
||||
0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16, 0
|
||||
0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16
|
||||
0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5
|
||||
0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20
|
||||
0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22
|
||||
|
|
|
|||
|
|
@ -110,3 +110,7 @@
|
|||
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
|
|
|
|||
|
|
@ -259,3 +259,11 @@
|
|||
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
|
||||
tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
|
||||
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
|
||||
mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
|
||||
mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
|
||||
mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
|
||||
mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
|
||||
mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
|
||||
mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
|
||||
mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
|
||||
mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
|
||||
|
|
|
|||
|
|
@ -138,3 +138,9 @@
|
|||
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
|
||||
dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
|
||||
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
|
||||
|
|
|
|||
|
|
@ -159,4 +159,17 @@ a:
|
|||
dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34]
|
||||
dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4]
|
||||
dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc]
|
||||
mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
|
||||
mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
|
||||
mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
|
||||
mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
|
||||
mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
|
||||
mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
|
||||
mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
|
||||
mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
|
||||
dmtc0 $15, $16 # CHECK: dmtc0 $15, $16, 0 # encoding: [0x59,0xf0,0x02,0xfc]
|
||||
dmtc0 $17, $18, 5 # CHECK: dmtc0 $17, $18, 5 # encoding: [0x5a,0x32,0x2a,0xfc]
|
||||
dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b]
|
||||
dmtc2 $21, $22 # CHECK: dmtc2 $21, $22 # encoding: [0x02,0xb6,0x7d,0x3c]
|
||||
|
||||
1:
|
||||
|
|
|
|||
Loading…
Reference in New Issue