forked from OSchip/llvm-project
R600: Implement float to long/ulong
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering
v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
add comment about using FP_TO_SINT for uints
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 212773
This commit is contained in:
Jan Vesely
parent
eca89d283e
commit
2cb62ce2a0
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@ -271,7 +271,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::ROTL, MVT::i64, Expand);
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setOperationAction(ISD::ROTR, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::MULHU, MVT::i64, Expand);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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@ -82,6 +82,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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@ -839,8 +841,20 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
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default:
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AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
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return;
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case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
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case ISD::FP_TO_UINT:
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if (N->getValueType(0) == MVT::i1) {
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Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
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return;
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}
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// Fall-through. Since we don't care about out of bounds values
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// we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
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// considers some extra cases which are not necessary here.
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case ISD::FP_TO_SINT: {
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SDValue Result;
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if (expandFP_TO_SINT(N, Result, DAG))
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Results.push_back(Result);
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return;
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}
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case ISD::UDIV: {
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SDValue Op = SDValue(N, 0);
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SDLoc DL(Op);
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@ -165,6 +165,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::LOAD, MVT::i1, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
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@ -1,31 +1,206 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; R600-CHECK: @fp_to_sint_v2i32
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; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI-CHECK: @fp_to_sint_v2i32
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; SI-CHECK: V_CVT_I32_F32_e32
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; SI-CHECK: V_CVT_I32_F32_e32
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; FUNC-LABEL: @fp_to_sint_v2i32
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: V_CVT_I32_F32_e32
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; SI: V_CVT_I32_F32_e32
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define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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%result = fptosi <2 x float> %in to <2 x i32>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @fp_to_sint_v4i32
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; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI-CHECK: @fp_to_sint_v4i32
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; SI-CHECK: V_CVT_I32_F32_e32
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; SI-CHECK: V_CVT_I32_F32_e32
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; SI-CHECK: V_CVT_I32_F32_e32
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; SI-CHECK: V_CVT_I32_F32_e32
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; FUNC-LABEL: @fp_to_sint_v4i32
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: V_CVT_I32_F32_e32
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; SI: V_CVT_I32_F32_e32
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; SI: V_CVT_I32_F32_e32
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; SI: V_CVT_I32_F32_e32
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define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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%result = fptosi <4 x float> %value to <4 x i32>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fp_to_sint_i64
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; Check that the compiler doesn't crash with a "cannot select" error
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; SI: S_ENDPGM
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define void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
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entry:
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%0 = fptosi float %in to i64
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; FUNC: @fp_to_sint_v2i64
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; SI: S_ENDPGM
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define void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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%conv = fptosi <2 x float> %x to <2 x i64>
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store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
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ret void
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}
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; FUNC: @fp_to_sint_v4i64
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; SI: S_ENDPGM
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define void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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%conv = fptosi <4 x float> %x to <4 x i64>
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store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
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ret void
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}
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@ -1,12 +0,0 @@
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; FIXME: Merge into fp_to_sint.ll when EG/NI supports 64-bit types
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s
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; SI-LABEL: @fp_to_sint_i64
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; Check that the compiler doesn't crash with a "cannot select" error
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; SI: S_ENDPGM
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define void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
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entry:
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%0 = fptosi float %in to i64
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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@ -1,12 +1,11 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; R600-CHECK: @fp_to_uint_v2i32
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; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-CHECK: @fp_to_uint_v2i32
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; SI-CHECK: V_CVT_U32_F32_e32
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; SI-CHECK: V_CVT_U32_F32_e32
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; FUNC-LABEL: @fp_to_uint_v2i32
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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%result = fptoui <2 x float> %in to <2 x i32>
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@ -14,16 +13,15 @@ define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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ret void
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}
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; R600-CHECK: @fp_to_uint_v4i32
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; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI-CHECK: @fp_to_uint_v4i32
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; SI-CHECK: V_CVT_U32_F32_e32
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; SI-CHECK: V_CVT_U32_F32_e32
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; SI-CHECK: V_CVT_U32_F32_e32
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; SI-CHECK: V_CVT_U32_F32_e32
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; FUNC-LABEL: @fp_to_uint_v4i32
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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@ -31,3 +29,179 @@ define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspac
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
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||||
|
||||
; FUNC: @fp_to_uint_i64
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
|
||||
; SI: S_ENDPGM
|
||||
define void @fp_to_uint_i64(i64 addrspace(1)* %out, float %x) {
|
||||
%conv = fptoui float %x to i64
|
||||
store i64 %conv, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC: @fp_to_uint_v2i64
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
|
||||
; SI: S_ENDPGM
|
||||
define void @fp_to_uint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
|
||||
%conv = fptoui <2 x float> %x to <2 x i64>
|
||||
store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC: @fp_to_uint_v4i64
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: ASHR
|
||||
; EG-DAG: AND_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: LSHL
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT
|
||||
; EG-DAG: SETGT_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: XOR_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: SUB_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
; EG-DAG: CNDGE_INT
|
||||
|
||||
; SI: S_ENDPGM
|
||||
define void @fp_to_uint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
|
||||
%conv = fptoui <4 x float> %x to <4 x i64>
|
||||
store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue