Only call isUse/isDef on register operands

llvm-svn: 30118
This commit is contained in:
Chris Lattner 2006-09-05 20:19:27 +00:00
parent 45456d44e3
commit 2cb238320d
2 changed files with 7 additions and 13 deletions

View File

@ -248,7 +248,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isUse() && MO.isRegister() && MO.getReg()) {
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@ -268,7 +268,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isDef() && MO.isRegister() && MO.getReg()) {
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());

View File

@ -158,7 +158,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
::print(getOperand(0), OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
@ -176,11 +176,8 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
OS << " ";
::print(mop, OS, TM);
if (mop.isDef())
if (mop.isUse())
OS << "<def&use>";
else
OS << "<def>";
if (mop.isReg() && mop.isDef())
OS << "<def>";
}
OS << "\n";
@ -204,11 +201,8 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
if (MI.getOperand(i).isDef())
if (MI.getOperand(i).isUse())
os << "<d&u>";
else
os << "<d>";
if (MI.getOperand(i).isReg() && MI.getOperand(i).isDef())
os << "<d>";
}
return os << "\n";