forked from OSchip/llvm-project
[SelectionDAG] Improve asserts in SelectionDAG::getSelect.
The VT passed in must match the type of LHS and RHS. Previously we only checked that the vectorness matched.
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@ -1103,10 +1103,8 @@ public:
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/// operands and don't want to check for vector.
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SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,
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SDValue RHS) {
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assert(LHS.getValueType() == RHS.getValueType() &&
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assert(LHS.getValueType() == VT && RHS.getValueType() == VT &&
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"Cannot use select on differing types");
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assert(VT.isVector() == LHS.getValueType().isVector() &&
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"Cannot mix vectors and scalars");
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auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
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return getNode(Opcode, DL, VT, Cond, LHS, RHS);
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}
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