forked from OSchip/llvm-project
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
llvm-svn: 103731
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@ -108,6 +108,11 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>;
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// Pseudo 256-bit registers to represent pairs of Q registers. These should
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// never be present in the emitted code.
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// These are used for NEON load / store instructions, e.g. vld4, vst3.
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// NOTE: It's possible to define more QQ registers since technical the
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// starting D register number doesn't have to be multiple of 4. e.g.
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// D1, D2, D3, D4 would be a legal quad. But that would make the sub-register
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// stuffs very messy.
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def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
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def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
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def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
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