forked from OSchip/llvm-project
X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we
were missing it on some movq instructions and were not including the appropriate PCrel bias. llvm-svn: 98880
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@ -166,7 +166,8 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
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// If the fixup is pc-relative, we need to bias the value to be relative to
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// the start of the field, not the end of the field.
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if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte))
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
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ImmOffset -= 4;
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if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
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ImmOffset -= 1;
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@ -203,7 +204,8 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// movq loads are handled with a special relocation form which allows the
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// linker to eliminate some loads for GOT references which end up in the
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// same linkage unit.
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if (MI.getOpcode() == X86::MOV64rm_TC)
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if (MI.getOpcode() == X86::MOV64rm ||
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MI.getOpcode() == X86::MOV64rm_TC)
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FixupKind = X86::reloc_riprel_4byte_movq_load;
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// rip-relative addressing is actually relative to the *next* instruction.
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@ -32,9 +32,14 @@ addq $-424, %rax
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// CHECK: movq _foo@GOTPCREL(%rip), %rax
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// CHECK: encoding: [0x48,0x8b,0x05,A,A,A,A]
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// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL, kind: reloc_riprel_4byte_movq_load
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// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
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movq _foo@GOTPCREL(%rip), %rax
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// CHECK: movq _foo@GOTPCREL(%rip), %r14
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// CHECK: encoding: [0x4c,0x8b,0x35,A,A,A,A]
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// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
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movq _foo@GOTPCREL(%rip), %r14
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// CHECK: movq (%r13,%rax,8), %r13
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// CHECK: encoding: [0x4d,0x8b,0x6c,0xc5,0x00]
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