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Add endprg, vid.v instruction definition

This commit is contained in:
Aries 2023-01-17 14:39:57 +08:00
parent 2515929e4e
commit 2c6aaa910c
2 changed files with 18 additions and 10 deletions
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12
llvm/lib/Target/RISCV/VentusInstrInfo.td
View File

@ -816,6 +816,8 @@ def OR : ALU_rr<0b0000000, 0b110, "or", /*Commutable*/1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def AND : ALU_rr<0b0000000, 0b111, "and", /*Commutable*/1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
// Ventus extended inst `endprg`
def ENDPRG : ALU_rr<0b0001011, 0b100, "endprg", 0>, Sched<[]>;
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
@ -929,16 +931,6 @@ def REGEXT : RVInstI<0b010, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPR:$rs1, simm12:$imm12),
"regext", "$rd, $rs1, $imm12">;
// imm12 is extended immediate from simm5 to support larger immediate
class ALU_ri_ventus<bits<3> funct3, string opcode> : RVInstI<funct3, OPC_CUSTOM_0,
(outs VGPR:$rd), (ins VGPR:$rs1, uimm12:$imm12),
"v" # opcode # "12.vi", "$rd, $rs1, $imm12">;
// vadd12.vi vd, vs1, imm
def VADDIMM12 : ALU_ri_ventus<0b000, "add">;
// vsub12.vi vd, vs1, imm
def VSUBIMM12 : ALU_ri_ventus<0b001, "sub">;
//===----------------------------------------------------------------------===//
// Privileged instructions
//===----------------------------------------------------------------------===//

16
llvm/lib/Target/RISCV/VentusInstrInfoV.td
View File

@ -743,6 +743,16 @@ def VSW : RVInstSetVLi<0, (outs), (ins VGPR:$vd, GPRMem:$rs1, simm11:$imm11),
}
let Predicates = [HasVInstructions] in {
// Ventus extended immediate12 vALU instructions
class VALU_ri12<bits<3> funct3, string opcode> :
RVInstI<funct3, OPC_CUSTOM_0,
(outs VGPR:$rd), (ins VGPR:$rs1, uimm12:$imm12),
"v" # opcode # "12.vi", "$rd, $rs1, $imm12">;
// vadd12.vi vd, vs1, imm
def VADDIMM12 : VALU_ri12<0b000, "add">;
// vsub12.vi vd, vs1, imm
def VSUBIMM12 : VALU_ri12<0b001, "sub">;
// Vector Single-Width Integer Add and Subtract
defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
@ -1103,6 +1113,12 @@ defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
let vs2 = 0 in
def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VGPR:$vd),
(ins), "vid.v", "$vd">,
Sched<[WriteVMIdxV]>;
// Integer Scalar Move Instructions
let RVVConstraint = NoConstraint in {
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),