forked from OSchip/llvm-project
Re-land "[MS] Overhaul how clang passes overaligned args on x86_32"
This brings back2af74e27edand revertseaabaf7e04. The changes were correct, the code that was broken contained an ODR violation that assumed that these types are passed equivalently: struct alignas(uint64_t) Wrapper { uint64_t P }; void f(uint64_t p); void f(Wrapper p); MSVC does not pass them the same way, and so clang-cl should not pass them the same way either.
This commit is contained in:
Reid Kleckner
parent
413307d456
commit
2c6a3896ab
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@ -88,6 +88,7 @@ private:
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Kind TheKind;
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bool PaddingInReg : 1;
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bool InAllocaSRet : 1; // isInAlloca()
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bool InAllocaIndirect : 1;// isInAlloca()
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bool IndirectByVal : 1; // isIndirect()
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bool IndirectRealign : 1; // isIndirect()
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bool SRetAfterThis : 1; // isIndirect()
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@ -110,8 +111,8 @@ private:
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public:
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ABIArgInfo(Kind K = Direct)
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: TypeData(nullptr), PaddingType(nullptr), DirectOffset(0),
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TheKind(K), PaddingInReg(false), InAllocaSRet(false),
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: TypeData(nullptr), PaddingType(nullptr), DirectOffset(0), TheKind(K),
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PaddingInReg(false), InAllocaSRet(false), InAllocaIndirect(false),
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IndirectByVal(false), IndirectRealign(false), SRetAfterThis(false),
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InReg(false), CanBeFlattened(false), SignExt(false) {}
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@ -185,9 +186,10 @@ public:
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AI.setInReg(true);
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return AI;
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}
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static ABIArgInfo getInAlloca(unsigned FieldIndex) {
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static ABIArgInfo getInAlloca(unsigned FieldIndex, bool Indirect = false) {
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auto AI = ABIArgInfo(InAlloca);
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AI.setInAllocaFieldIndex(FieldIndex);
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AI.setInAllocaIndirect(Indirect);
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return AI;
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}
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static ABIArgInfo getExpand() {
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@ -380,6 +382,15 @@ public:
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AllocaFieldIndex = FieldIndex;
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}
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unsigned getInAllocaIndirect() const {
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assert(isInAlloca() && "Invalid kind!");
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return InAllocaIndirect;
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}
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void setInAllocaIndirect(bool Indirect) {
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assert(isInAlloca() && "Invalid kind!");
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InAllocaIndirect = Indirect;
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}
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/// Return true if this field of an inalloca struct should be returned
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/// to implement a struct return calling convention.
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bool getInAllocaSRet() const {
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@ -2370,6 +2370,9 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI,
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auto FieldIndex = ArgI.getInAllocaFieldIndex();
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Address V =
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Builder.CreateStructGEP(ArgStruct, FieldIndex, Arg->getName());
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if (ArgI.getInAllocaIndirect())
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V = Address(Builder.CreateLoad(V),
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getContext().getTypeAlignInChars(Ty));
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ArgVals.push_back(ParamValue::forIndirect(V));
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break;
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}
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@ -4091,18 +4094,39 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo,
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assert(NumIRArgs == 0);
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assert(getTarget().getTriple().getArch() == llvm::Triple::x86);
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if (I->isAggregate()) {
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// Replace the placeholder with the appropriate argument slot GEP.
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Address Addr = I->hasLValue()
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? I->getKnownLValue().getAddress(*this)
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: I->getKnownRValue().getAggregateAddress();
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llvm::Instruction *Placeholder =
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cast<llvm::Instruction>(Addr.getPointer());
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CGBuilderTy::InsertPoint IP = Builder.saveIP();
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Builder.SetInsertPoint(Placeholder);
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Addr =
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Builder.CreateStructGEP(ArgMemory, ArgInfo.getInAllocaFieldIndex());
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Builder.restoreIP(IP);
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if (!ArgInfo.getInAllocaIndirect()) {
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// Replace the placeholder with the appropriate argument slot GEP.
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CGBuilderTy::InsertPoint IP = Builder.saveIP();
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Builder.SetInsertPoint(Placeholder);
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Addr = Builder.CreateStructGEP(ArgMemory,
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ArgInfo.getInAllocaFieldIndex());
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Builder.restoreIP(IP);
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} else {
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// For indirect things such as overaligned structs, replace the
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// placeholder with a regular aggregate temporary alloca. Store the
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// address of this alloca into the struct.
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Addr = CreateMemTemp(info_it->type, "inalloca.indirect.tmp");
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Address ArgSlot = Builder.CreateStructGEP(
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ArgMemory, ArgInfo.getInAllocaFieldIndex());
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Builder.CreateStore(Addr.getPointer(), ArgSlot);
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}
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deferPlaceholderReplacement(Placeholder, Addr.getPointer());
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} else if (ArgInfo.getInAllocaIndirect()) {
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// Make a temporary alloca and store the address of it into the argument
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// struct.
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Address Addr = CreateMemTempWithoutCast(
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I->Ty, getContext().getTypeAlignInChars(I->Ty),
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"indirect-arg-temp");
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I->copyInto(*this, Addr);
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Address ArgSlot =
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Builder.CreateStructGEP(ArgMemory, ArgInfo.getInAllocaFieldIndex());
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Builder.CreateStore(Addr.getPointer(), ArgSlot);
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} else {
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// Store the RValue into the argument struct.
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Address Addr =
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@ -1702,6 +1702,7 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;
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Ty = useFirstFieldIfTransparentUnion(Ty);
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TypeInfo TI = getContext().getTypeInfo(Ty);
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// Check with the C++ ABI first.
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const RecordType *RT = Ty->getAs<RecordType>();
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@ -1751,7 +1752,7 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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bool NeedsPadding = false;
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bool InReg;
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if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
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unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
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unsigned SizeInRegs = (TI.Width + 31) / 32;
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SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
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llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
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if (InReg)
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@ -1761,14 +1762,19 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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}
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llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
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// Pass over-aligned aggregates on Windows indirectly. This behavior was
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// added in MSVC 2015.
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if (IsWin32StructABI && TI.AlignIsRequired && TI.Align > 32)
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return getIndirectResult(Ty, /*ByVal=*/false, State);
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// Expand small (<= 128-bit) record types when we know that the stack layout
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// of those arguments will match the struct. This is important because the
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// LLVM backend isn't smart enough to remove byval, which inhibits many
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// optimizations.
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// Don't do this for the MCU if there are still free integer registers
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// (see X86_64 ABI for full explanation).
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if (getContext().getTypeSize(Ty) <= 4 * 32 &&
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(!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
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if (TI.Width <= 4 * 32 && (!IsMCUABI || State.FreeRegs == 0) &&
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canExpandIndirectArgument(Ty))
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return ABIArgInfo::getExpandWithPadding(
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IsFastCall || IsVectorCall || IsRegCall, PaddingType);
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@ -1776,14 +1782,24 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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}
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if (const VectorType *VT = Ty->getAs<VectorType>()) {
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// On Windows, vectors are passed directly if registers are available, or
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// indirectly if not. This avoids the need to align argument memory. Pass
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// user-defined vector types larger than 512 bits indirectly for simplicity.
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if (IsWin32StructABI) {
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if (TI.Width <= 512 && State.FreeSSERegs > 0) {
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--State.FreeSSERegs;
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return ABIArgInfo::getDirectInReg();
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}
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return getIndirectResult(Ty, /*ByVal=*/false, State);
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}
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// On Darwin, some vectors are passed in memory, we handle this by passing
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// it as an i8/i16/i32/i64.
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if (IsDarwinVectorABI) {
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uint64_t Size = getContext().getTypeSize(Ty);
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if ((Size == 8 || Size == 16 || Size == 32) ||
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(Size == 64 && VT->getNumElements() == 1))
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return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
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Size));
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if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) ||
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(TI.Width == 64 && VT->getNumElements() == 1))
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return ABIArgInfo::getDirect(
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llvm::IntegerType::get(getVMContext(), TI.Width));
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}
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if (IsX86_MMXType(CGT.ConvertType(Ty)))
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@ -1813,9 +1829,10 @@ void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
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CCState State(FI);
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if (IsMCUABI)
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State.FreeRegs = 3;
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else if (State.CC == llvm::CallingConv::X86_FastCall)
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else if (State.CC == llvm::CallingConv::X86_FastCall) {
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State.FreeRegs = 2;
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else if (State.CC == llvm::CallingConv::X86_VectorCall) {
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State.FreeSSERegs = 3;
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} else if (State.CC == llvm::CallingConv::X86_VectorCall) {
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State.FreeRegs = 2;
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State.FreeSSERegs = 6;
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} else if (FI.getHasRegParm())
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@ -1823,6 +1840,11 @@ void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
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else if (State.CC == llvm::CallingConv::X86_RegCall) {
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State.FreeRegs = 5;
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State.FreeSSERegs = 8;
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} else if (IsWin32StructABI) {
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// Since MSVC 2015, the first three SSE vectors have been passed in
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// registers. The rest are passed indirectly.
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State.FreeRegs = DefaultNumRegisterParameters;
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State.FreeSSERegs = 3;
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} else
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State.FreeRegs = DefaultNumRegisterParameters;
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@ -1869,16 +1891,25 @@ X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
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CharUnits &StackOffset, ABIArgInfo &Info,
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QualType Type) const {
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// Arguments are always 4-byte-aligned.
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CharUnits FieldAlign = CharUnits::fromQuantity(4);
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CharUnits WordSize = CharUnits::fromQuantity(4);
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assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct");
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assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
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Info = ABIArgInfo::getInAlloca(FrameFields.size());
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FrameFields.push_back(CGT.ConvertTypeForMem(Type));
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StackOffset += getContext().getTypeSizeInChars(Type);
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// sret pointers and indirect things will require an extra pointer
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// indirection, unless they are byval. Most things are byval, and will not
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// require this indirection.
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bool IsIndirect = false;
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if (Info.isIndirect() && !Info.getIndirectByVal())
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IsIndirect = true;
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Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect);
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llvm::Type *LLTy = CGT.ConvertTypeForMem(Type);
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if (IsIndirect)
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LLTy = LLTy->getPointerTo(0);
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FrameFields.push_back(LLTy);
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StackOffset += IsIndirect ? WordSize : getContext().getTypeSizeInChars(Type);
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// Insert padding bytes to respect alignment.
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CharUnits FieldEnd = StackOffset;
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StackOffset = FieldEnd.alignTo(FieldAlign);
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StackOffset = FieldEnd.alignTo(WordSize);
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if (StackOffset != FieldEnd) {
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CharUnits NumBytes = StackOffset - FieldEnd;
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llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
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@ -1892,16 +1923,12 @@ static bool isArgInAlloca(const ABIArgInfo &Info) {
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switch (Info.getKind()) {
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case ABIArgInfo::InAlloca:
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return true;
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case ABIArgInfo::Indirect:
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assert(Info.getIndirectByVal());
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return true;
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case ABIArgInfo::Ignore:
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return false;
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case ABIArgInfo::Indirect:
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case ABIArgInfo::Direct:
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case ABIArgInfo::Extend:
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if (Info.getInReg())
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return false;
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return true;
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return !Info.getInReg();
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case ABIArgInfo::Expand:
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case ABIArgInfo::CoerceAndExpand:
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// These are aggregate types which are never passed in registers when
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@ -1935,8 +1962,7 @@ void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
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// Put the sret parameter into the inalloca struct if it's in memory.
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if (Ret.isIndirect() && !Ret.getInReg()) {
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CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
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addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
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addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
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// On Windows, the hidden sret parameter is always returned in eax.
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Ret.setInAllocaSRet(IsWin32StructABI);
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}
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@ -46,3 +46,47 @@ struct s6 {
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struct s6 f6_1(void) { while (1) {} }
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void f6_2(struct s6 a0) {}
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// MSVC passes up to three vectors in registers, and the rest indirectly. We
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// (arbitrarily) pass oversized vectors indirectly, since that is the safest way
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// to do it.
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typedef float __m128 __attribute__((__vector_size__(16), __aligned__(16)));
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typedef float __m256 __attribute__((__vector_size__(32), __aligned__(32)));
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typedef float __m512 __attribute__((__vector_size__(64), __aligned__(64)));
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typedef float __m1024 __attribute__((__vector_size__(128), __aligned__(128)));
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__m128 gv128;
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__m256 gv256;
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__m512 gv512;
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__m1024 gv1024;
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void receive_vec_128(__m128 x, __m128 y, __m128 z, __m128 w, __m128 q) {
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gv128 = x + y + z + w + q;
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}
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void receive_vec_256(__m256 x, __m256 y, __m256 z, __m256 w, __m256 q) {
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gv256 = x + y + z + w + q;
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}
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void receive_vec_512(__m512 x, __m512 y, __m512 z, __m512 w, __m512 q) {
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gv512 = x + y + z + w + q;
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}
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void receive_vec_1024(__m1024 x, __m1024 y, __m1024 z, __m1024 w, __m1024 q) {
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gv1024 = x + y + z + w + q;
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}
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// CHECK-LABEL: define dso_local void @receive_vec_128(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* %0, <4 x float>* %1)
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// CHECK-LABEL: define dso_local void @receive_vec_256(<8 x float> inreg %x, <8 x float> inreg %y, <8 x float> inreg %z, <8 x float>* %0, <8 x float>* %1)
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// CHECK-LABEL: define dso_local void @receive_vec_512(<16 x float> inreg %x, <16 x float> inreg %y, <16 x float> inreg %z, <16 x float>* %0, <16 x float>* %1)
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// CHECK-LABEL: define dso_local void @receive_vec_1024(<32 x float>* %0, <32 x float>* %1, <32 x float>* %2, <32 x float>* %3, <32 x float>* %4)
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void pass_vec_128() {
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__m128 z = {0};
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receive_vec_128(z, z, z, z, z);
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}
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// CHECK-LABEL: define dso_local void @pass_vec_128()
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// CHECK: call void @receive_vec_128(<4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float>* %{{[^,)]*}}, <4 x float>* %{{[^,)]*}})
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void __fastcall fastcall_indirect_vec(__m128 x, __m128 y, __m128 z, __m128 w, int edx, __m128 q) {
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gv128 = x + y + z + w + q;
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}
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// CHECK-LABEL: define dso_local x86_fastcallcc void @"\01@fastcall_indirect_vec@84"(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* inreg %0, i32 inreg %edx, <4 x float>* %1)
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@ -0,0 +1,52 @@
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// RUN: %clang_cc1 -fms-extensions -w -triple i386-pc-win32 -emit-llvm -o - %s | FileCheck %s
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// PR44395
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// MSVC passes overaligned types indirectly since MSVC 2015. Make sure that
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// works with inalloca.
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// FIXME: Pass non-trivial *and* overaligned types indirectly. Right now the C++
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// ABI rules say to use inalloca, and they take precedence, so it's not easy to
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// implement this.
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struct NonTrivial {
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NonTrivial();
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NonTrivial(const NonTrivial &o);
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int x;
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};
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struct __declspec(align(64)) OverAligned {
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OverAligned();
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int buf[16];
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};
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extern int gvi32;
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int receive_inalloca_overaligned(NonTrivial nt, OverAligned o) {
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return nt.x + o.buf[0];
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}
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// CHECK-LABEL: define dso_local i32 @"?receive_inalloca_overaligned@@Y{{.*}}"
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// CHECK-SAME: (<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca %0)
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int pass_inalloca_overaligned() {
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gvi32 = receive_inalloca_overaligned(NonTrivial(), OverAligned());
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return gvi32;
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}
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// CHECK-LABEL: define dso_local i32 @"?pass_inalloca_overaligned@@Y{{.*}}"
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// CHECK: [[TMP:%[^ ]*]] = alloca %struct.OverAligned, align 64
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// CHECK: call i8* @llvm.stacksave()
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// CHECK: alloca inalloca <{ %struct.NonTrivial, %struct.OverAligned* }>
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// Construct OverAligned into TMP.
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// CHECK: call x86_thiscallcc %struct.OverAligned* @"??0OverAligned@@QAE@XZ"(%struct.OverAligned* [[TMP]])
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// Construct NonTrivial into the GEP.
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// CHECK: [[GEP:%[^ ]*]] = getelementptr inbounds <{ %struct.NonTrivial, %struct.OverAligned* }>, <{ %struct.NonTrivial, %struct.OverAligned* }>* %{{.*}}, i32 0, i32 0
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// CHECK: call x86_thiscallcc %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* [[GEP]])
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// Store the address of an OverAligned temporary into the struct.
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// CHECK: getelementptr inbounds <{ %struct.NonTrivial, %struct.OverAligned* }>, <{ %struct.NonTrivial, %struct.OverAligned* }>* %{{.*}}, i32 0, i32 1
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// CHECK: store %struct.OverAligned* [[TMP]], %struct.OverAligned** %{{.*}}, align 4
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// CHECK: call i32 @"?receive_inalloca_overaligned@@Y{{.*}}"(<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca %argmem)
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@ -0,0 +1,79 @@
|
|||
// RUN: %clang_cc1 -w -triple i686-pc-win32 -emit-llvm -o - %s | FileCheck %s
|
||||
|
||||
// PR44395
|
||||
// MSVC passes up to three vectors in registers, and the rest indirectly. Check
|
||||
// that both are compatible with an inalloca prototype.
|
||||
|
||||
struct NonTrivial {
|
||||
NonTrivial();
|
||||
NonTrivial(const NonTrivial &o);
|
||||
unsigned handle;
|
||||
};
|
||||
|
||||
typedef float __m128 __attribute__((__vector_size__(16), __aligned__(16)));
|
||||
__m128 gv128;
|
||||
|
||||
// nt, w, and q will be in the inalloca pack.
|
||||
void receive_vec_128(NonTrivial nt, __m128 x, __m128 y, __m128 z, __m128 w, __m128 q) {
|
||||
gv128 = x + y + z + w + q;
|
||||
}
|
||||
// CHECK-LABEL: define dso_local void @"?receive_vec_128@@YAXUNonTrivial@@T__m128@@1111@Z"
|
||||
// CHECK-SAME: (<4 x float> inreg %x,
|
||||
// CHECK-SAME: <4 x float> inreg %y,
|
||||
// CHECK-SAME: <4 x float> inreg %z,
|
||||
// CHECK-SAME: <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* inalloca %0)
|
||||
|
||||
void pass_vec_128() {
|
||||
__m128 z = {0};
|
||||
receive_vec_128(NonTrivial(), z, z, z, z, z);
|
||||
}
|
||||
// CHECK-LABEL: define dso_local void @"?pass_vec_128@@YAXXZ"()
|
||||
// CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 0
|
||||
// CHECK: call x86_thiscallcc %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* %{{.*}})
|
||||
|
||||
// Store q, store temp alloca.
|
||||
// CHECK: store <4 x float> %{{[^,]*}}, <4 x float>* %{{[^,]*}}, align 16
|
||||
// CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 1
|
||||
// CHECK: store <4 x float>* %{{[^,]*}}, <4 x float>** %{{[^,]*}}, align 4
|
||||
|
||||
// Store w, store temp alloca.
|
||||
// CHECK: store <4 x float> %{{[^,]*}}, <4 x float>* %{{[^,]*}}, align 16
|
||||
// CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 2
|
||||
// CHECK: store <4 x float>* %{{[^,]*}}, <4 x float>** %{{[^,]*}}, align 4
|
||||
|
||||
// CHECK: call void @"?receive_vec_128@@YAXUNonTrivial@@T__m128@@1111@Z"
|
||||
// CHECK-SAME: (<4 x float> inreg %{{[^,]*}},
|
||||
// CHECK-SAME: <4 x float> inreg %{{[^,]*}},
|
||||
// CHECK-SAME: <4 x float> inreg %{{[^,]*}},
|
||||
// CHECK-SAME: <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* inalloca %{{[^,]*}})
|
||||
|
||||
// w will be passed indirectly by register, and q will be passed indirectly, but
|
||||
// the pointer will be in memory.
|
||||
void __fastcall fastcall_receive_vec(__m128 x, __m128 y, __m128 z, __m128 w, int edx, __m128 q, NonTrivial nt) {
|
||||
gv128 = x + y + z + w + q;
|
||||
}
|
||||
// CHECK-LABEL: define dso_local x86_fastcallcc void @"?fastcall_receive_vec@@Y{{[^"]*}}"
|
||||
// CHECK-SAME: (<4 x float> inreg %x,
|
||||
// CHECK-SAME: <4 x float> inreg %y,
|
||||
// CHECK-SAME: <4 x float> inreg %z,
|
||||
// CHECK-SAME: <4 x float>* inreg %0,
|
||||
// CHECK-SAME: i32 inreg %edx,
|
||||
// CHECK-SAME: <{ <4 x float>*, %struct.NonTrivial }>* inalloca %1)
|
||||
|
||||
|
||||
void __vectorcall vectorcall_receive_vec(double xmm0, double xmm1, double xmm2,
|
||||
__m128 x, __m128 y, __m128 z,
|
||||
__m128 w, int edx, __m128 q, NonTrivial nt) {
|
||||
gv128 = x + y + z + w + q;
|
||||
}
|
||||
// FIXME: Enable these checks, clang generates wrong IR.
|
||||
// CHECK-LABEL: define dso_local x86_vectorcallcc void @"?vectorcall_receive_vec@@Y{{[^"]*}}"
|
||||
// CHECKX-SAME: (double inreg %xmm0,
|
||||
// CHECKX-SAME: double inreg %xmm1,
|
||||
// CHECKX-SAME: double inreg %xmm2,
|
||||
// CHECKX-SAME: <4 x float> inreg %x,
|
||||
// CHECKX-SAME: <4 x float> inreg %y,
|
||||
// CHECKX-SAME: <4 x float> inreg %z,
|
||||
// CHECKX-SAME: <4 x float>* inreg %0,
|
||||
// CHECKX-SAME: i32 inreg %edx,
|
||||
// CHECKX-SAME: <{ <4 x float>*, %struct.NonTrivial }>* inalloca %1)
|
||||
Loading…
Reference in New Issue