forked from OSchip/llvm-project
parent
bb2a6da440
commit
2c67006cdd
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@ -64,5 +64,5 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(hasMips64() ?
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&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass);
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return OptLevel >= CodeGenOpt::Default;
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return OptLevel >= CodeGenOpt::Aggressive;
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}
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