forked from OSchip/llvm-project
ARM assembly parsing and encoding for VST2 single-element, double spaced.
llvm-svn: 146990
This commit is contained in:
Jim Grosbach
parent
72a05a9198
commit
2c59052984
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@ -5800,6 +5800,10 @@ defm VST2LNdAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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@ -5807,6 +5811,10 @@ defm VST2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdWB_register_Asm :
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NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
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@ -5819,6 +5827,14 @@ defm VST2LNdWB_register_Asm :
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NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VST2LNqWB_register_Asm :
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NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VST2LNqWB_register_Asm :
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NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VMOV takes an optional datatype suffix
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defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
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@ -5118,84 +5118,134 @@ validateInstruction(MCInst &Inst,
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return false;
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}
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static unsigned getRealVSTLNOpcode(unsigned Opc) {
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static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) {
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switch(Opc) {
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default: assert(0 && "unexpected opcode!");
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// VST1LN
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case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
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case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
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case ARM::VST1LNdWB_fixed_Asm_U8:
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Spacing = 1;
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return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16:
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case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16:
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case ARM::VST1LNdWB_fixed_Asm_U16:
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Spacing = 1;
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return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
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case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
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case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32:
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Spacing = 1;
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return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
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case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
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case ARM::VST1LNdWB_register_Asm_U8:
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Spacing = 1;
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return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16:
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case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16:
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case ARM::VST1LNdWB_register_Asm_U16:
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Spacing = 1;
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return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
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case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
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case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32:
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Spacing = 1;
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return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8:
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case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8:
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case ARM::VST1LNdAsm_U8:
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Spacing = 1;
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return ARM::VST1LNd8;
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case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16:
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case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
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case ARM::VST1LNdAsm_U16:
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Spacing = 1;
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return ARM::VST1LNd16;
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case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
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case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32:
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case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32:
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Spacing = 1;
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return ARM::VST1LNd32;
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// VST2LN
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case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
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case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
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case ARM::VST2LNdWB_fixed_Asm_U8:
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Spacing = 1;
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return ARM::VST2LNd8_UPD;
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case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16:
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case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16:
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case ARM::VST2LNdWB_fixed_Asm_U16:
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Spacing = 1;
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return ARM::VST2LNd16_UPD;
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case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
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case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
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case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
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Spacing = 1;
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return ARM::VST2LNd32_UPD;
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case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
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case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
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case ARM::VST2LNqWB_fixed_Asm_U16:
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Spacing = 2;
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return ARM::VST2LNq16_UPD;
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case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F:
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case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32:
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case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32:
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Spacing = 2;
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return ARM::VST2LNq32_UPD;
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case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
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case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
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case ARM::VST2LNdWB_register_Asm_U8:
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Spacing = 1;
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return ARM::VST2LNd8_UPD;
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case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16:
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case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16:
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case ARM::VST2LNdWB_register_Asm_U16:
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Spacing = 1;
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return ARM::VST2LNd16_UPD;
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case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
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case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
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case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
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Spacing = 1;
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return ARM::VST2LNd32_UPD;
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case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
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case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
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case ARM::VST2LNqWB_register_Asm_U16:
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Spacing = 2;
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return ARM::VST2LNq16_UPD;
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case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F:
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case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32:
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case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32:
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Spacing = 2;
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return ARM::VST2LNq32_UPD;
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case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8:
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case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8:
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case ARM::VST2LNdAsm_U8:
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Spacing = 1;
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return ARM::VST2LNd8;
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case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16:
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case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
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case ARM::VST2LNdAsm_U16:
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Spacing = 1;
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return ARM::VST2LNd16;
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case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
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case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32:
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case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32:
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Spacing = 1;
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return ARM::VST2LNd32;
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case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
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case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16:
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case ARM::VST2LNqAsm_U16:
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Spacing = 2;
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return ARM::VST2LNq16;
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case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F:
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case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32:
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case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:
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Spacing = 2;
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return ARM::VST2LNq32;
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}
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}
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@ -5344,7 +5394,8 @@ processInstruction(MCInst &Inst,
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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@ -5357,24 +5408,32 @@ processInstruction(MCInst &Inst,
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return true;
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}
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case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
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case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
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case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
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case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
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case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
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case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
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case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16:
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case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16:
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case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
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case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
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case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
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case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: {
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case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
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case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
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case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
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case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32:
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case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32:
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case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32:
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case ARM::VST2LNqWB_register_Asm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(4)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(5)); // CondCode
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TmpInst.addOperand(Inst.getOperand(6));
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@ -5392,7 +5451,8 @@ processInstruction(MCInst &Inst,
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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@ -5405,24 +5465,32 @@ processInstruction(MCInst &Inst,
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return true;
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}
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case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
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case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
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case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
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case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
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case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
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case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
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case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16:
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case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16:
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case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
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case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
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case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
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case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: {
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case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
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case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
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case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
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case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32:
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case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32:
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case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32:
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case ARM::VST2LNqWB_fixed_Asm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(1)); // lane
|
||||
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
|
||||
TmpInst.addOperand(Inst.getOperand(5));
|
||||
|
|
@ -5438,7 +5506,8 @@ processInstruction(MCInst &Inst,
|
|||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // alignment
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
|
|
@ -5449,20 +5518,25 @@ processInstruction(MCInst &Inst,
|
|||
return true;
|
||||
}
|
||||
|
||||
case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
|
||||
case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
|
||||
case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
|
||||
case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
|
||||
case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
|
||||
case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
|
||||
case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
|
||||
case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32:
|
||||
case ARM::VST2LNdAsm_U32: {
|
||||
case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
|
||||
case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16:
|
||||
case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32:
|
||||
case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
|
||||
unsigned Spacing;
|
||||
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(2)); // Rn
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // alignment
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Vd
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
|
||||
Spacing));
|
||||
TmpInst.addOperand(Inst.getOperand(1)); // lane
|
||||
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
|
||||
TmpInst.addOperand(Inst.getOperand(5));
|
||||
|
|
@ -5504,11 +5578,12 @@ processInstruction(MCInst &Inst,
|
|||
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
|
||||
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
|
||||
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
|
||||
case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16:
|
||||
case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16:
|
||||
case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
|
||||
case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
|
||||
case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: {
|
||||
case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
|
||||
case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
|
||||
case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32:
|
||||
case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32:
|
||||
case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32:
|
||||
case ARM::VLD2LNqWB_register_Asm_U32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
|
|
@ -5565,11 +5640,12 @@ processInstruction(MCInst &Inst,
|
|||
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: {
|
||||
case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_U32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
|
|
@ -5592,10 +5668,10 @@ processInstruction(MCInst &Inst,
|
|||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
|
||||
case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
|
||||
case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
|
||||
case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
|
||||
case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
|
||||
case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
|
||||
case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
|
||||
case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32:
|
||||
case ARM::VLD1LNdAsm_U32: {
|
||||
MCInst TmpInst;
|
||||
|
|
|
|||
|
|
@ -101,23 +101,37 @@
|
|||
vst2.8 {d16[1], d17[1]}, [r0, :16]
|
||||
vst2.16 {d16[1], d17[1]}, [r0, :32]
|
||||
vst2.32 {d16[1], d17[1]}, [r0]
|
||||
@ vst2.16 {d17[1], d19[1]}, [r0]
|
||||
@ vst2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
vst2.16 {d17[1], d19[1]}, [r0]
|
||||
vst2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
|
||||
vst2.8 {d2[4], d3[4]}, [r2], r3
|
||||
vst2.8 {d2[4], d3[4]}, [r2]!
|
||||
vst2.8 {d2[4], d3[4]}, [r2]
|
||||
|
||||
vst2.16 {d17[1], d19[1]}, [r0]
|
||||
vst2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
vst2.16 {d7[1], d9[1]}, [r1]!
|
||||
vst2.32 {d6[0], d8[0]}, [r2, :64]!
|
||||
vst2.16 {d2[1], d4[1]}, [r3], r5
|
||||
vst2.32 {d5[0], d7[0]}, [r4, :64], r7
|
||||
|
||||
@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
|
||||
@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
|
||||
@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4]
|
||||
@ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
|
||||
@ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
|
||||
@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
|
||||
@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
|
||||
|
||||
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4]
|
||||
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4]
|
||||
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4]
|
||||
|
||||
@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
|
||||
@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
|
||||
@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4]
|
||||
@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4]
|
||||
@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4]
|
||||
@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
|
||||
|
||||
|
||||
@ vst3.8 {d16[1], d17[1], d18[1]}, [r0]
|
||||
@ vst3.16 {d16[1], d17[1], d18[1]}, [r0]
|
||||
|
|
|
|||
Loading…
Reference in New Issue