forked from OSchip/llvm-project
get rid of some non-DebugLoc getTargetNode variants.
llvm-svn: 63909
This commit is contained in:
parent
74b5ef7cae
commit
2c4cf2752d
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@ -683,33 +683,16 @@ public:
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
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MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
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const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
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const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2);
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2);
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SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2, SDValue Op3);
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2, SDValue Op3);
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SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
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const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
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const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
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const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
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MVT VT4, const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
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const SDValue *Ops, unsigned NumOps);
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SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
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const std::vector<MVT> &ResultTys, const SDValue *Ops,
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unsigned NumOps);
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@ -4506,11 +4506,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
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return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
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const SDValue *Ops, unsigned NumOps) {
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const MVT *VTs = getNodeValueTypes(VT1, VT2);
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return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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MVT VT1, MVT VT2,
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const SDValue *Ops, unsigned NumOps) {
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@ -4518,12 +4513,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2) {
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const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
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SDValue Ops[] = { Op1, Op2 };
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return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2) {
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@ -4532,13 +4521,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2,
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SDValue Op3) {
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const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
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SDValue Ops[] = { Op1, Op2, Op3 };
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return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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MVT VT1, MVT VT2, MVT VT3,
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SDValue Op1, SDValue Op2,
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@ -4548,11 +4530,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
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const SDValue *Ops, unsigned NumOps) {
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const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
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return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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MVT VT1, MVT VT2, MVT VT3,
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const SDValue *Ops, unsigned NumOps) {
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@ -4560,17 +4537,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
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MVT VT2, MVT VT3, MVT VT4,
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const SDValue *Ops, unsigned NumOps) {
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std::vector<MVT> VTList;
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VTList.push_back(VT1);
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VTList.push_back(VT2);
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VTList.push_back(VT3);
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VTList.push_back(VT4);
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const MVT *VTs = getNodeValueTypes(VTList);
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return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
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MVT VT2, MVT VT3, MVT VT4,
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const SDValue *Ops, unsigned NumOps) {
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@ -4583,13 +4549,6 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
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return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
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const std::vector<MVT> &ResultTys,
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const SDValue *Ops, unsigned NumOps) {
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const MVT *VTs = getNodeValueTypes(ResultTys);
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return getNode(~Opcode, VTs, ResultTys.size(),
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Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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const std::vector<MVT> &ResultTys,
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const SDValue *Ops, unsigned NumOps) {
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@ -717,7 +717,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
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SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
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SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
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MVT::Flag, Ops, 5);
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Chain = SDValue(ResNode, 0);
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if (Op.getNode()->getNumValues() == 2) {
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InFlag = SDValue(ResNode, 1);
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@ -158,6 +158,7 @@ InstructionSelect() {
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SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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MVT NVT = N->getValueType(0);
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if (NVT == MVT::i32) {
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switch (N->getOpcode()) {
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@ -165,26 +166,27 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
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case ISD::Constant: {
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if (Predicate_immMskBitp(N)) {
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SDValue MskSize = Transform_msksize_xform(N);
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return CurDAG->getTargetNode(XCore::MKMSK_rus, MVT::i32, MskSize);
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return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize);
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}
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else if (! Predicate_immU16(N)) {
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unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
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SDValue CPIdx =
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CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
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TLI.getPointerTy());
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return CurDAG->getTargetNode(XCore::LDWCP_lru6, MVT::i32, MVT::Other,
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CPIdx, CurDAG->getEntryNode());
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return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, MVT::i32,
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MVT::Other, CPIdx,
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CurDAG->getEntryNode());
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}
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break;
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}
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case ISD::SMUL_LOHI: {
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// FIXME fold addition into the macc instruction
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if (!Subtarget.isXS1A()) {
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SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, MVT::i32,
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SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
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CurDAG->getTargetConstant(0, MVT::i32)), 0);
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SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
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SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, MVT::i32,
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MVT::i32, Ops, 4);
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SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, dl,
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MVT::i32, MVT::i32, Ops, 4);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
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return NULL;
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@ -193,11 +195,11 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
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}
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case ISD::UMUL_LOHI: {
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// FIXME fold addition into the macc / lmul instruction
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SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, MVT::i32,
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SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
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CurDAG->getTargetConstant(0, MVT::i32)), 0);
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SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
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Zero, Zero };
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SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, MVT::i32,
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SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, MVT::i32,
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MVT::i32, Ops, 4);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
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@ -207,7 +209,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
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if (!Subtarget.isXS1A()) {
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SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
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Op.getOperand(2) };
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return CurDAG->getTargetNode(XCore::LADD_l5r, MVT::i32, MVT::i32,
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return CurDAG->getTargetNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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break;
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@ -216,7 +218,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
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if (!Subtarget.isXS1A()) {
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SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
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Op.getOperand(2) };
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return CurDAG->getTargetNode(XCore::LSUB_l5r, MVT::i32, MVT::i32,
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return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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break;
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