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[AArch64][SVE] Asm: Support for SEL (vector/predicate) instructions. 

Support for SVE's predicated select instructions to select elements
from either vector, both in a data-vector and a predicate-vector
variant.

llvm-svn: 334905
This commit is contained in:
Sander de Smalen 2018-06-17 10:11:04 +00:00
parent c7410ed47a
commit 2c25b4cd36
4 changed files with 185 additions and 0 deletions
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7
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View File

@ -57,6 +57,11 @@ let Predicates = [HasSVE] in {
defm CPY_ZPmR : sve_int_perm_cpy_r<"cpy">;
defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">;
// Select elements from either vector (predicated)
defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
def SEL_PPPP : sve_int_pred_log<0b0011, "sel">;
// continuous load with reg+immediate
defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
@ -504,4 +509,6 @@ let Predicates = [HasSVE] in {
// InstAliases
def : InstAlias<"mov $Zd, $Zn",
(ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
def : InstAlias<"mov $Pd, $Pg/m, $Pn",
(SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
}

74
llvm/lib/Target/AArch64/SVEInstrFormats.td
View File

@ -411,6 +411,80 @@ multiclass sve_int_perm_dup_i<string asm> {
(!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
}
//===----------------------------------------------------------------------===//
// SVE Vector Select Group
//===----------------------------------------------------------------------===//
class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
asm, "\t$Zd, $Pg, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<4> Pg;
bits<5> Zd;
bits<5> Zm;
bits<5> Zn;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-14} = 0b11;
let Inst{13-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve_int_sel_vvv<string asm> {
def _B : sve_int_sel_vvv<0b00, asm, ZPR8>;
def _H : sve_int_sel_vvv<0b01, asm, ZPR16>;
def _S : sve_int_sel_vvv<0b10, asm, ZPR32>;
def _D : sve_int_sel_vvv<0b11, asm, ZPR64>;
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>;
}
//===----------------------------------------------------------------------===//
// SVE Predicate Logical Operations Group
//===----------------------------------------------------------------------===//
class sve_int_pred_log<bits<4> opc, string asm>
: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
asm, "\t$Pd, $Pg/z, $Pn, $Pm",
"",
[]>, Sched<[]> {
bits<4> Pd;
bits<4> Pg;
bits<4> Pm;
bits<4> Pn;
let Inst{31-24} = 0b00100101;
let Inst{23-22} = opc{3-2};
let Inst{21-20} = 0b00;
let Inst{19-16} = Pm;
let Inst{15-14} = 0b01;
let Inst{13-10} = Pg;
let Inst{9} = opc{1};
let Inst{8-5} = Pn;
let Inst{4} = opc{0};
let Inst{3-0} = Pd;
// SEL has no predication qualifier.
let AsmString = !if(!eq(opc, 0b0011),
!strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"),
!strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm"));
let Defs = !if(!eq (opc{2}, 1), [NZCV], []);
}
//===----------------------------------------------------------------------===//
// SVE Logical Mask Immediate Group
//===----------------------------------------------------------------------===//

36
llvm/test/MC/AArch64/SVE/mov.s
View File

@ -600,3 +600,39 @@ mov z31.d, p7/m, d31
// CHECK-ENCODING: [0xff,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f e0 05 <unknown>
mov p0.b, p0/m, p0.b
// CHECK-INST: mov p0.b, p0/m, p0.b
// CHECK-ENCODING: [0x10,0x42,0x00,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 10 42 00 25 <unknown>
mov p15.b, p15/m, p15.b
// CHECK-INST: mov p15.b, p15/m, p15.b
// CHECK-ENCODING: [0xff,0x7f,0x0f,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 7f 0f 25 <unknown>
mov z31.b, p15/m, z31.b
// CHECK-INST: mov z31.b, p15/m, z31.b
// CHECK-ENCODING: [0xff,0xff,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 3f 05 <unknown>
mov z31.h, p15/m, z31.h
// CHECK-INST: mov z31.h, p15/m, z31.h
// CHECK-ENCODING: [0xff,0xff,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 7f 05 <unknown>
mov z31.s, p15/m, z31.s
// CHECK-INST: mov z31.s, p15/m, z31.s
// CHECK-ENCODING: [0xff,0xff,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff bf 05 <unknown>
mov z31.d, p15/m, z31.d
// CHECK-INST: mov z31.d, p15/m, z31.d
// CHECK-ENCODING: [0xff,0xff,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff ff 05 <unknown>

68
llvm/test/MC/AArch64/SVE/sel.s Normal file
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@ -0,0 +1,68 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sel p0.b, p0, p0.b, p0.b
// CHECK-INST: mov p0.b, p0/m, p0.b
// CHECK-ENCODING: [0x10,0x42,0x00,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 10 42 00 25 <unknown>
sel p15.b, p15, p15.b, p15.b
// CHECK-INST: mov p15.b, p15/m, p15.b
// CHECK-ENCODING: [0xff,0x7f,0x0f,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 7f 0f 25 <unknown>
sel z31.b, p15, z31.b, z31.b
// CHECK-INST: mov z31.b, p15/m, z31.b
// CHECK-ENCODING: [0xff,0xff,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 3f 05 <unknown>
sel z31.h, p15, z31.h, z31.h
// CHECK-INST: mov z31.h, p15/m, z31.h
// CHECK-ENCODING: [0xff,0xff,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 7f 05 <unknown>
sel z31.s, p15, z31.s, z31.s
// CHECK-INST: mov z31.s, p15/m, z31.s
// CHECK-ENCODING: [0xff,0xff,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff bf 05 <unknown>
sel z31.d, p15, z31.d, z31.d
// CHECK-INST: mov z31.d, p15/m, z31.d
// CHECK-ENCODING: [0xff,0xff,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff ff 05 <unknown>
sel z23.s, p11, z13.s, z8.s
// CHECK-INST: sel z23.s, p11, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0xed,0xa8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed a8 05 <unknown>
sel z23.d, p11, z13.d, z8.d
// CHECK-INST: sel z23.d, p11, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0xed,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed e8 05 <unknown>
sel z23.h, p11, z13.h, z8.h
// CHECK-INST: sel z23.h, p11, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xed,0x68,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed 68 05 <unknown>
sel z23.b, p11, z13.b, z8.b
// CHECK-INST: sel z23.b, p11, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0xed,0x28,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed 28 05 <unknown>