forked from OSchip/llvm-project
[InstCombine] canonicalize select with signbit test
This is part of solving issue #54750 - in that example we have both forms of the compare and do not recognize the equivalence.
This commit is contained in:
Sanjay Patel
parent
5193f2a558
commit
2c2568f39e
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@ -1602,6 +1602,23 @@ Instruction *InstCombinerImpl::foldSelectInstWithICmp(SelectInst &SI,
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}
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}
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// Canonicalize a signbit condition to use zero constant by swapping:
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// (CmpLHS > -1) ? TV : FV --> (CmpLHS < 0) ? FV : TV
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// To avoid conflicts (infinite loops) with other canonicalizations, this is
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// not applied with any constant select arm.
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if (Pred == ICmpInst::ICMP_SGT && match(CmpRHS, m_AllOnes()) &&
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!match(TrueVal, m_Constant()) && !match(FalseVal, m_Constant()) &&
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ICI->hasOneUse()) {
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InstCombiner::BuilderTy::InsertPointGuard Guard(Builder);
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Builder.SetInsertPoint(&SI);
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Value *IsNeg = Builder.CreateICmpSLT(
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CmpLHS, ConstantInt::getNullValue(CmpLHS->getType()), ICI->getName());
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replaceOperand(SI, 0, IsNeg);
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SI.swapValues();
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SI.swapProfMetadata();
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return &SI;
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}
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// FIXME: This code is nearly duplicated in InstSimplify. Using/refactoring
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// decomposeBitTestICmp() might help.
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{
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@ -3,8 +3,8 @@
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define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_exact_ashr_only(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP12]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, %y
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@ -15,8 +15,8 @@ define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
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define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_no_exact(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP12]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, %y
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@ -27,8 +27,8 @@ define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
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define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_exact_both(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP12]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr exact i32 %x, %y
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@ -39,8 +39,8 @@ define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
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define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP12]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr exact i32 %x, %y
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@ -63,8 +63,8 @@ define i32 @ashr_lshr2(i32 %x, i32 %y) {
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define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP12]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr <2 x i32> %x, %y
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@ -75,8 +75,8 @@ define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec2(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP12]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr exact <2 x i32> %x, %y
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@ -87,8 +87,8 @@ define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec3(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP12]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr exact <2 x i32> %x, %y
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@ -99,8 +99,8 @@ define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec4(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP12]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr <2 x i32> %x, %y
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@ -171,8 +171,8 @@ define i32 @ashr_lshr_cst(i32 %x, i32 %y) {
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define i32 @ashr_lshr_cst2(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_cst2(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], 8
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; CHECK-NEXT: ret i32 [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], 8
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; CHECK-NEXT: ret i32 [[CMP12]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, 8
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@ -231,8 +231,8 @@ define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_vec_undef(
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP12]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
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%l = lshr <2 x i32> %x, %y
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@ -317,10 +317,10 @@ define i32 @ashr_lshr_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
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define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_shift_wrong_pred2(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Z:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[Z:%.*]], 0
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %z, 0
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@ -332,10 +332,10 @@ define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
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define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_wrong_operands(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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@ -347,10 +347,10 @@ define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) {
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define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_no_ashr(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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@ -362,10 +362,10 @@ define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) {
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define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_shift_amt_mismatch(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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@ -377,10 +377,10 @@ define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
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define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_shift_base_mismatch(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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@ -392,10 +392,10 @@ define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
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define i32 @ashr_lshr_no_lshr(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_no_lshr(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[L:%.*]] = add i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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@ -422,10 +422,10 @@ define <2 x i32> @ashr_lshr_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_inv_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_inv_vec_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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;
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%cmp = icmp sge <2 x i32> %x, zeroinitializer
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@ -758,10 +758,10 @@ define <2 x i16> @bitcast_vec_cond_commute3(<4 x i8> %cond, <2 x i16> %pc, <2 x
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; CHECK-LABEL: @bitcast_vec_cond_commute3(
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; CHECK-NEXT: [[C:%.*]] = mul <2 x i16> [[PC:%.*]], [[PC]]
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; CHECK-NEXT: [[D:%.*]] = mul <2 x i16> [[PD:%.*]], [[PD]]
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; CHECK-NEXT: [[DOTNOT:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[D]] to <4 x i8>
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[C]] to <4 x i8>
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; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[DOTNOT]], <4 x i8> [[TMP2]], <4 x i8> [[TMP1]]
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; CHECK-NEXT: [[DOTNOT2:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[DOTNOT2]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[TMP4]]
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;
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@ -111,8 +111,8 @@ define i16 @testtrunclowhigh(i32 %add, i16 %low, i16 %high) {
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; CHECK-NEXT: [[A:%.*]] = add i32 [[ADD:%.*]], 128
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[A]], 256
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; CHECK-NEXT: [[T:%.*]] = trunc i32 [[ADD]] to i16
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; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[ADD]], -1
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; CHECK-NEXT: [[F:%.*]] = select i1 [[C]], i16 [[HIGH:%.*]], i16 [[LOW:%.*]]
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; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[ADD]], 0
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; CHECK-NEXT: [[F:%.*]] = select i1 [[C1]], i16 [[LOW:%.*]], i16 [[HIGH:%.*]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i16 [[T]], i16 [[F]]
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; CHECK-NEXT: ret i16 [[R]]
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;
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