From 2c0956bcea0c352a8f72b2e68b1a186b103c9ab8 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 4 Feb 2006 06:58:46 +0000 Subject: [PATCH] Two changes: 1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode 2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end up with commented out copies! This should fix a bunch of failures in V9 mode on sparc. llvm-svn: 25961 --- llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp | 23 ++++++++++--------- llvm/lib/Target/SparcV8/SparcV8InstrInfo.h | 2 +- .../Target/SparcV8/SparcV8RegisterInfo.cpp | 9 +++++--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h | 5 +++- .../Target/SparcV8/SparcV8TargetMachine.cpp | 2 +- 5 files changed, 24 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp index 6faa9723c162..cddeddd9b826 100644 --- a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp +++ b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp @@ -17,12 +17,13 @@ #include "SparcV8GenInstrInfo.inc" using namespace llvm; -SparcV8InstrInfo::SparcV8InstrInfo() - : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){ +SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST) + : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])), + RI(ST) { } -static bool isZeroImmed (const MachineOperand &op) { - return (op.isImmediate() && op.getImmedValue() == 0); +static bool isZeroImm(const MachineOperand &op) { + return op.isImmediate() && op.getImmedValue() == 0; } /// Return true if the instruction is a register to register move and @@ -44,13 +45,13 @@ bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI, SrcReg = MI.getOperand(1).getReg(); return true; } - } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) { - if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) { + } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri && + isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) { + DstReg = MI.getOperand(0).getReg(); + SrcReg = MI.getOperand(1).getReg(); + return true; + } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD || + MI.getOpcode() == V8::FMOVD) { SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; diff --git a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.h b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.h index 067fb91cb264..0b2ee905e364 100644 --- a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.h +++ b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.h @@ -34,7 +34,7 @@ namespace V8II { class SparcV8InstrInfo : public TargetInstrInfo { const SparcV8RegisterInfo RI; public: - SparcV8InstrInfo(); + SparcV8InstrInfo(SparcV8Subtarget &ST); /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should diff --git a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp index dc7979f0627a..abbf11f06b4e 100644 --- a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp +++ b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp @@ -13,6 +13,7 @@ #include "SparcV8.h" #include "SparcV8RegisterInfo.h" +#include "SparcV8Subtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -21,9 +22,10 @@ #include using namespace llvm; -SparcV8RegisterInfo::SparcV8RegisterInfo() +SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st) : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, - V8::ADJCALLSTACKUP) {} + V8::ADJCALLSTACKUP), Subtarget(st) { +} void SparcV8RegisterInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, @@ -63,7 +65,8 @@ void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, else if (RC == V8::FPRegsRegisterClass) BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg); else if (RC == V8::DFPRegsRegisterClass) - BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg); + BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD, + 1, DestReg).addReg(SrcReg); else assert (0 && "Can't copy this register"); } diff --git a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h index 784a8e5c805c..f739551f8693 100644 --- a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h +++ b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h @@ -19,10 +19,13 @@ namespace llvm { +class SparcV8Subtarget; class Type; struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo { - SparcV8RegisterInfo(); + SparcV8Subtarget &Subtarget; + + SparcV8RegisterInfo(SparcV8Subtarget &st); /// Code Generation virtual methods... void storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp index 88f88f4acdee..d868c10042f3 100644 --- a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp +++ b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp @@ -35,7 +35,7 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL, const std::string &FS) : TargetMachine("SparcV8", IL, false, 4, 4), - Subtarget(M, FS), + Subtarget(M, FS), InstrInfo(Subtarget), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { }