forked from OSchip/llvm-project
[x86] Remove the final fallback in the v8i16 lowering that isn't really
needed, and significantly improve the SSSE3 path. This makes the new strategy much more clear. If we can blend, we just go with that. If we can't blend, we try to permute into an unpack so that we handle cases where the unpack doing the blend also simplifies the shuffle. If that fails and we've got SSSE3, we now call into factored-out pshufb lowering code so that we leverage the fact that pshufb can set up a blend for us while shuffling. This generates great code, especially because we *know* we don't have a fast blend at this point. Finally, we fall back on decomposing into permutes and blends because we do at least have a bit-math-based blend if we need to use that. This pretty significantly improves some of the v8i16 code paths. We never need to form pshufb for the single-input shuffles because we have effective target-specific combines to form it there, but we were missing its effectiveness in the blends. llvm-svn: 229851
This commit is contained in:
Chandler Carruth
parent
5b5c7cec08
commit
2c0390ca4b
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@ -9637,6 +9637,58 @@ static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
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DAG.getUNDEF(MVT::v8i16), Mask);
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}
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/// \brief Helper to form a PSHUFB-based shuffle+blend.
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static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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SelectionDAG &DAG, bool &V1InUse,
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bool &V2InUse) {
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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SDValue V1Mask[16];
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SDValue V2Mask[16];
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V1InUse = false;
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V2InUse = false;
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int Size = Mask.size();
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int Scale = 16 / Size;
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for (int i = 0; i < 16; ++i) {
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if (Mask[i / Scale] == -1) {
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V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
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} else {
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const int ZeroMask = 0x80;
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int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
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: ZeroMask;
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int V2Idx = Mask[i / Scale] < Size
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? ZeroMask
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: (Mask[i / Scale] - Size) * Scale + i % Scale;
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if (Zeroable[i / Scale])
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V1Idx = V2Idx = ZeroMask;
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V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
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V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
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V1InUse |= (ZeroMask != V1Idx);
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V2InUse |= (ZeroMask != V2Idx);
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}
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}
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if (V1InUse)
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V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
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DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
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if (V2InUse)
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V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
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DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
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// If we need shuffled inputs from both, blend the two.
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SDValue V;
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if (V1InUse && V2InUse)
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V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
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else
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V = V1InUse ? V1 : V2;
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// Cast the result back to the correct type.
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return DAG.getNode(ISD::BITCAST, DL, VT, V);
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}
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/// \brief Generic lowering of 8-lane i16 shuffles.
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///
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/// This handles both single-input shuffles and combined shuffle/blends with
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@ -9746,32 +9798,26 @@ static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
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}
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// If we have direct support for blends, we should lower by decomposing into
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// a permute.
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if (IsBlendSupported)
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return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
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Mask, DAG);
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// Try to lower by permuting the inputs into an unpack instruction unless we
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// have direct support for blending.
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if (!IsBlendSupported) {
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if (SDValue Unpack =
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lowerVectorShuffleAsUnpack(MVT::v8i16, DL, V1, V2, Mask, DAG))
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return Unpack;
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// Try to lower by permuting the inputs into an unpack instruction.
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if (SDValue Unpack =
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lowerVectorShuffleAsUnpack(MVT::v8i16, DL, V1, V2, Mask, DAG))
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return Unpack;
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int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
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int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
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for (int i = 0; i < 4; ++i) {
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LoBlendMask[i] = Mask[i];
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HiBlendMask[i] = Mask[i + 4];
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// If we can use PSHUFB, that will be better as it can both shuffle and set
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// up an efficient blend.
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if (Subtarget->hasSSSE3()) {
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bool V1InUse, V2InUse;
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return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
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V1InUse, V2InUse);
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}
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}
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SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
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SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
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LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
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HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
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return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
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DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
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// We can always bit-blend if we have to so the fallback strategy is to
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// decompose into single-input permutes and blends.
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return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
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Mask, DAG);
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}
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/// \brief Check whether a compaction lowering can be done by dropping even
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@ -10002,27 +10048,11 @@ static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// interleavings with direct instructions supporting them. We currently don't
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// handle those well here.
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if (Subtarget->hasSSSE3()) {
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SDValue V1Mask[16];
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SDValue V2Mask[16];
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bool V1InUse = false;
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bool V2InUse = false;
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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for (int i = 0; i < 16; ++i) {
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if (Mask[i] == -1) {
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V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
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} else {
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const int ZeroMask = 0x80;
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int V1Idx = (Mask[i] < 16 ? Mask[i] : ZeroMask);
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int V2Idx = (Mask[i] < 16 ? ZeroMask : Mask[i] - 16);
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if (Zeroable[i])
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V1Idx = V2Idx = ZeroMask;
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V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
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V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
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V1InUse |= (ZeroMask != V1Idx);
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V2InUse |= (ZeroMask != V2Idx);
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}
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}
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SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
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DAG, V1InUse, V2InUse);
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// If both V1 and V2 are in use and we can use a direct blend or an unpack,
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// do so. This avoids using them to handle blends-with-zero which is
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@ -10046,22 +10076,7 @@ static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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return Unpack;
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}
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if (V1InUse)
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V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
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if (V2InUse)
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V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
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// If we need shuffled inputs from both, blend the two.
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if (V1InUse && V2InUse)
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return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
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if (V1InUse)
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return V1; // Single inputs are easy.
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if (V2InUse)
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return V2; // Single inputs are easy.
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// Shuffling to a zeroable vector.
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return getZeroVector(MVT::v16i8, Subtarget, DAG, DL);
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return PSHUFB;
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}
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// There are special ways we can lower some single-element blends.
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@ -41,11 +41,11 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
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; X64-LABEL: t2:
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; X64: ## BB#0:
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
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; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
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; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,0,3,4,5,6,7]
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; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; X64-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,0,65535,65535,65535,65535]
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; X64-NEXT: pand %xmm2, %xmm0
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; X64-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,1,2,1,4,5,6,7]
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; X64-NEXT: pandn %xmm1, %xmm2
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; X64-NEXT: por %xmm2, %xmm0
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; X64-NEXT: retq
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
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ret <8 x i16> %tmp
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@ -1100,27 +1100,27 @@ define <16 x i8> @shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00(
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: movdqa %xmm0, %xmm3
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
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; SSE2-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[3,1,2,3]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm3[3,1,2,3]
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; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
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; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,3,0,1]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,1,2,2,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5,7,7]
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; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [65535,65535,65535,0,65535,0,0,65535]
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,3,1,3,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6,4]
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; SSE2-NEXT: pand %xmm5, %xmm2
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; SSE2-NEXT: pandn %xmm4, %xmm5
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; SSE2-NEXT: por %xmm2, %xmm5
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[3,1,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm0[1,1,2,3,4,5,6,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[2,1,0,3,4,5,6,7]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm0[0,2,2,1,4,5,6,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm3[0,1,2,3,6,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,1,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,0,2,1,4,5,6,7]
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm5[1,1,2,3,4,5,6,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1],xmm4[2],xmm0[2],xmm4[3],xmm0[3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm4[0,2,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[2,1,0,3,4,5,6,7]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm5[0,2,2,1,4,5,6,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3]
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; SSE2-NEXT: packuswb %xmm2, %xmm3
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; SSE2-NEXT: packuswb %xmm5, %xmm3
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; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]
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; SSE2-NEXT: pand %xmm0, %xmm3
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
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@ -1267,29 +1267,21 @@ define <8 x i16> @shuffle_v8i16_cde3XXXX(<8 x i16> %a, <8 x i16> %b) {
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define <8 x i16> @shuffle_v8i16_012dcde3(<8 x i16> %a, <8 x i16> %b) {
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; SSE2-LABEL: shuffle_v8i16_012dcde3:
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; SSE2: # BB#0:
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,7,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,1]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,1,2,0,4,5,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,2,0,3,4,5,6,7]
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,5,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,1]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,3,0,2,4,5,6,7]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v8i16_012dcde3:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,8,9,14,15,12,13,14,15]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,6,7,8,9,0,1,0,1,2,3]
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[10,11,8,9,10,11,12,13],zero,zero
|
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],zero,zero,zero,zero,zero,zero,zero,zero,xmm0[6,7]
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; SSSE3-NEXT: por %xmm1, %xmm0
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; SSSE3-NEXT: retq
|
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;
|
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; SSE41-LABEL: shuffle_v8i16_012dcde3:
|
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|
|
|
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Loading…
Reference in New Issue