From 2bf8e3e0e191bd434b867133d0ee093eec63edfb Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 26 Feb 2018 02:16:33 +0000 Subject: [PATCH] [X86] Simplify the ReplaceNodeResults code for X86ISD::AVG. This code seemed to try to widen to 128, 256, or 512 bit vectors, but we only create X86ISD::AVG with a power of 2 number of elements. This means the only nodes that need to be legalized are less than 128-bits and need to be widened up to 128 bits. llvm-svn: 326064 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f2a88ef6f5ce..e1fc9a2d5144 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24828,19 +24828,13 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); auto InVT = N->getValueType(0); - auto InVTSize = InVT.getSizeInBits(); - const unsigned RegSize = - (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128; - assert((Subtarget.hasBWI() || RegSize < 512) && - "512-bit vector requires AVX512BW"); - assert((Subtarget.hasAVX2() || RegSize < 256) && - "256-bit vector requires AVX2"); + assert(InVT.getSizeInBits() < 128); + assert(128 % InVT.getSizeInBits() == 0); + unsigned NumConcat = 128 / InVT.getSizeInBits(); - auto ElemVT = InVT.getVectorElementType(); - auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, - RegSize / ElemVT.getSizeInBits()); - assert(RegSize % InVT.getSizeInBits() == 0); - unsigned NumConcat = RegSize / InVT.getSizeInBits(); + EVT RegVT = EVT::getVectorVT(*DAG.getContext(), + InVT.getVectorElementType(), + NumConcat * InVT.getVectorNumElements()); SmallVector Ops(NumConcat, DAG.getUNDEF(InVT)); Ops[0] = N->getOperand(0);