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[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner 

When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc
have the same type (creates COPY) use Src register directly or
use replaceRegOrBuildCopy instead.

Differential Revision: https://reviews.llvm.org/D108306
This commit is contained in:
Petar Avramovic 2021-08-24 11:09:37 +02:00
parent b52171629f
commit 2bf4eeeeb6
216 changed files with 14236 additions and 27997 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
View File

@ -54,7 +54,8 @@ public:
bool tryCombineAnyExt(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts,
SmallVectorImpl<Register> &UpdatedDefs) {
SmallVectorImpl<Register> &UpdatedDefs,
GISelObserverWrapper &Observer) {
assert(MI.getOpcode() == TargetOpcode::G_ANYEXT);
Builder.setInstrAndDebugLoc(MI);
@ -65,7 +66,11 @@ public:
Register TruncSrc;
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
if (MRI.getType(DstReg) == MRI.getType(TruncSrc))
replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs,
Observer);
else
Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
UpdatedDefs.push_back(DstReg);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
@ -125,9 +130,11 @@ public:
APInt MaskVal = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
auto Mask = Builder.buildConstant(
DstTy, MaskVal.zext(DstTy.getScalarSizeInBits()));
auto Extended = SextSrc ? Builder.buildSExtOrTrunc(DstTy, SextSrc) :
Builder.buildAnyExtOrTrunc(DstTy, TruncSrc);
Builder.buildAnd(DstReg, Extended, Mask);
if (SextSrc && (DstTy != MRI.getType(SextSrc)))
SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0);
if (TruncSrc && (DstTy != MRI.getType(TruncSrc)))
TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
Builder.buildAnd(DstReg, SextSrc ? SextSrc : TruncSrc, Mask);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
@ -178,9 +185,9 @@ public:
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg);
uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
Builder.buildInstr(
TargetOpcode::G_SEXT_INREG, {DstReg},
{Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), SizeInBits});
if (DstTy != MRI.getType(TruncSrc))
TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
@ -1078,7 +1085,7 @@ public:
default:
return false;
case TargetOpcode::G_ANYEXT:
Changed = tryCombineAnyExt(MI, DeadInsts, UpdatedDefs);
Changed = tryCombineAnyExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);
break;
case TargetOpcode::G_ZEXT:
Changed = tryCombineZExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);

38
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
View File

@ -329,7 +329,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB6_1
; CHECK-NOLSE-O0-NEXT: b LBB6_1
; CHECK-NOLSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB6_2 Depth 2
@ -540,7 +540,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1
; CHECK-NOLSE-O0-NEXT: LBB8_5
; CHECK-NOLSE-O0-NEXT: b LBB8_5
; CHECK-NOLSE-O0-NEXT: LBB8_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@ -1649,7 +1649,7 @@ define i8 @atomicrmw_or_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB31_1
; CHECK-NOLSE-O0-NEXT: b LBB31_5
; CHECK-NOLSE-O0-NEXT: b LBB31_5
; CHECK-NOLSE-O0-NEXT: LBB31_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@ -1765,8 +1765,7 @@ define i8 @atomicrmw_min_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxtb w9, w10
; CHECK-NOLSE-O0-NEXT: mov w12, w8
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, sxtb
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, sxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, le
; CHECK-NOLSE-O0-NEXT: LBB33_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB33_1 Depth=1
@ -1836,8 +1835,7 @@ define i8 @atomicrmw_max_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxtb w9, w10
; CHECK-NOLSE-O0-NEXT: mov w12, w8
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, sxtb
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, sxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, gt
; CHECK-NOLSE-O0-NEXT: LBB34_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB34_1 Depth=1
@ -1907,8 +1905,7 @@ define i8 @atomicrmw_umin_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: and w9, w10, #0xff
; CHECK-NOLSE-O0-NEXT: mov w12, w8
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, uxtb
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ls
; CHECK-NOLSE-O0-NEXT: LBB35_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB35_1 Depth=1
@ -1928,7 +1925,7 @@ define i8 @atomicrmw_umin_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB35_1
; CHECK-NOLSE-O0-NEXT: b LBB35_5
; CHECK-NOLSE-O0-NEXT: b LBB35_5
; CHECK-NOLSE-O0-NEXT: LBB35_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@ -1978,8 +1975,7 @@ define i8 @atomicrmw_umax_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: and w9, w10, #0xff
; CHECK-NOLSE-O0-NEXT: mov w12, w8
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, uxtb
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, hi
; CHECK-NOLSE-O0-NEXT: LBB36_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB36_1 Depth=1
@ -2448,8 +2444,7 @@ define i16 @atomicrmw_min_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxth w10, w8
; CHECK-NOLSE-O0-NEXT: mov w12, w9
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, sxth
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, le
; CHECK-NOLSE-O0-NEXT: LBB43_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB43_1 Depth=1
@ -2519,8 +2514,7 @@ define i16 @atomicrmw_max_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxth w10, w8
; CHECK-NOLSE-O0-NEXT: mov w12, w9
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, sxth
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, gt
; CHECK-NOLSE-O0-NEXT: LBB44_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB44_1 Depth=1
@ -2590,8 +2584,7 @@ define i16 @atomicrmw_umin_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: uxth w10, w8
; CHECK-NOLSE-O0-NEXT: mov w12, w9
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, uxth
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ls
; CHECK-NOLSE-O0-NEXT: LBB45_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB45_1 Depth=1
@ -2661,8 +2654,7 @@ define i16 @atomicrmw_umax_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: uxth w10, w8
; CHECK-NOLSE-O0-NEXT: mov w12, w9
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, uxth
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, hi
; CHECK-NOLSE-O0-NEXT: LBB46_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB46_1 Depth=1
@ -2729,10 +2721,9 @@ define { i8, i1 } @cmpxchg_i8(i8* %ptr, i8 %desired, i8 %new) {
; CHECK-NOLSE-O0-LABEL: cmpxchg_i8:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: mov x9, x0
; CHECK-NOLSE-O0-NEXT: mov w10, w1
; CHECK-NOLSE-O0-NEXT: LBB47_1: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ldaxrb w0, [x9]
; CHECK-NOLSE-O0-NEXT: cmp w0, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cmp w0, w1, uxtb
; CHECK-NOLSE-O0-NEXT: b.ne LBB47_3
; CHECK-NOLSE-O0-NEXT: ; %bb.2: ; in Loop: Header=BB47_1 Depth=1
; CHECK-NOLSE-O0-NEXT: stlxrb w8, w2, [x9]
@ -2796,10 +2787,9 @@ define { i16, i1 } @cmpxchg_i16(i16* %ptr, i16 %desired, i16 %new) {
; CHECK-NOLSE-O0-LABEL: cmpxchg_i16:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: mov x9, x0
; CHECK-NOLSE-O0-NEXT: mov w10, w1
; CHECK-NOLSE-O0-NEXT: LBB48_1: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ldaxrh w0, [x9]
; CHECK-NOLSE-O0-NEXT: cmp w0, w10, uxth
; CHECK-NOLSE-O0-NEXT: cmp w0, w1, uxth
; CHECK-NOLSE-O0-NEXT: b.ne LBB48_3
; CHECK-NOLSE-O0-NEXT: ; %bb.2: ; in Loop: Header=BB48_1 Depth=1
; CHECK-NOLSE-O0-NEXT: stlxrh w8, w2, [x9]

11
llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
View File

@ -10,10 +10,8 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY3]](s64)
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: $x0 = COPY [[COPY]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@ -71,10 +69,9 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
; CHECK: G_STORE [[COPY2]](s64), %ptr(p0) :: (store (s64), align 16)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s64)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
; CHECK: G_STORE [[COPY3]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
; CHECK: G_STORE [[TRUNC]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
; CHECK: G_STORE [[LSHR2]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
%ptr:_(p0) = COPY $x0
%a:_(s88) = G_LOAD %ptr(p0) :: (load (s88))

6
llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
View File

@ -20,8 +20,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic (s8) on %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMICRMW_ADD]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s8) on %ir.addr)
@ -39,8 +38,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic (s16) on %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMICRMW_ADD]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 1
%2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s16) on %ir.addr)

6
llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
View File

@ -12,12 +12,10 @@ body: |
; CHECK-LABEL: name: bswap_s16
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[LSHR]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %1(s32)

13
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
View File

@ -8,20 +8,17 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[ICMP1]](s32)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
; CHECK: $w0 = COPY [[ICMP2]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x0
%2:_(s8) = G_TRUNC %0(s64)
@ -53,9 +50,7 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ICMP2]], [[ICMP]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32)
; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.1
; CHECK: G_BR %bb.2

27
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
View File

@ -17,13 +17,12 @@ body: |
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic (s64) on %ir.addr)
; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s32), [[CMP]]
; CHECK: [[SRES32:%[0-9]+]]:_(s32) = COPY [[SRES]]
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[RES]], [[SRES32]]
; CHECK: $w0 = COPY [[MUL]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64) on %ir.addr)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s32), [[C]]
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ATOMIC_CMPXCHG]], [[ICMP]]
; CHECK: $w0 = COPY [[MUL]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_CONSTANT i32 1
@ -42,13 +41,13 @@ body: |
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic (s64) on %ir.addr)
; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s64), [[CMP]]
; CHECK: [[SRES64:%[0-9]+]]:_(s64) = G_ANYEXT [[SRES]]
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[RES]], [[SRES64]]
; CHECK: $x0 = COPY [[MUL]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64) on %ir.addr)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s64), [[C]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ATOMIC_CMPXCHG]], [[ANYEXT]]
; CHECK: $x0 = COPY [[MUL]](s64)
%0:_(p0) = COPY $x0
%1:_(s64) = G_CONSTANT i64 0
%2:_(s64) = G_CONSTANT i64 1

6
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
View File

@ -21,8 +21,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s8) on %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMIC_CMPXCHG]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 0
%2:_(s8) = G_CONSTANT i8 1
@ -42,8 +41,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s16) on %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMIC_CMPXCHG]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG]](s32)
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 0
%2:_(s16) = G_CONSTANT i16 1

7
llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
View File

@ -22,10 +22,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: $x0 = COPY [[COPY2]](s64)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0

12
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
View File

@ -120,8 +120,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s16) = G_TRUNC %copy(s32)
@ -148,8 +147,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s8) = G_TRUNC %copy(s32)
@ -176,8 +174,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s3) = G_TRUNC %copy(s32)
@ -203,8 +200,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s8) = G_TRUNC %copy(s32)

6
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
View File

@ -16,8 +16,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s8) = G_IMPLICIT_DEF
%cttz:_(s8) = G_CTTZ_ZERO_UNDEF %val(s8)
@ -40,8 +39,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = G_IMPLICIT_DEF
%cttz:_(s16) = G_CTTZ_ZERO_UNDEF %val(s16)

6
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
View File

@ -16,8 +16,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s8) = G_IMPLICIT_DEF
%cttz:_(s8) = G_CTTZ %val(s8)
@ -40,8 +39,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = G_IMPLICIT_DEF
%cttz:_(s16) = G_CTTZ %val(s16)

6
llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
View File

@ -12,16 +12,14 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[SDIV]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[UDIV]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)

15
llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
View File

@ -54,15 +54,12 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w1 = COPY [[COPY6]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[MUL]]
; CHECK: $w0 = COPY [[SDIV]](s32)
; CHECK: $w1 = COPY [[SUB]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)

25
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
View File

@ -14,16 +14,12 @@ body: |
; CHECK: $w0 = COPY [[TRUNC2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC3]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: $x0 = COPY [[AND]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY3]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY4]], 32
; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK: $x0 = COPY [[SEXT_INREG]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1
@ -53,8 +49,8 @@ body: |
; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
; CHECK: $x0 = COPY [[FPEXT]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: $w0 = COPY [[COPY5]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[C3]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[DEF]](s32)
@ -117,8 +113,7 @@ body: |
; CHECK-LABEL: name: test_anyext_anyext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s8) = G_ANYEXT %1(s1)
@ -134,8 +129,7 @@ body: |
; CHECK-LABEL: name: test_anyext_sext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
@ -153,8 +147,7 @@ body: |
; CHECK-LABEL: name: test_anyext_zext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)

15
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
View File

@ -28,14 +28,12 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]]
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[ASHR]](<2 x s64>), [[COPY2]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[EVEC]](s64)
; CHECK: $x0 = COPY [[COPY4]](s64)
; CHECK: $x0 = COPY [[EVEC]](s64)
; CHECK: RET_ReallyLR
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
@ -56,10 +54,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]]
; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ICMP]](<4 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<4 x s32>)
; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<4 x s32>)
; CHECK: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<4 x s32>)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ASHR]](<4 x s32>), [[COPY2]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EVEC]](s32)
@ -84,10 +81,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]]
; CHECK: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ICMP]](<8 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; CHECK: [[SHL:%[0-9]+]]:_(<8 x s16>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<8 x s16>)
; CHECK: [[SHL:%[0-9]+]]:_(<8 x s16>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<8 x s16>)
; CHECK: [[ASHR:%[0-9]+]]:_(<8 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<8 x s16>)
; CHECK: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[ASHR]](<8 x s16>), [[COPY2]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EVEC]](s16)
@ -112,10 +108,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<16 x s8>)
; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<16 x s8>)
; CHECK: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<16 x s8>)
; CHECK: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[ASHR]](<16 x s8>), [[COPY2]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EVEC]](s8)

12
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
View File

@ -239,8 +239,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %val(s32)
; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: %ext:_(s32) = G_AND %val, [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
@ -259,8 +258,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %val(s32)
; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: %ext:_(s32) = G_AND %val, [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
@ -278,9 +276,8 @@ body: |
; CHECK-LABEL: name: s3_from_s35
; CHECK: liveins: $w0
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
; CHECK: %ext:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
@ -300,8 +297,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %val(s32)
; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: %ext:_(s32) = G_AND %val, [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0

15
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
View File

@ -139,8 +139,7 @@ body: |
; CHECK-LABEL: name: test_fptoui_s1_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@ -155,8 +154,7 @@ body: |
; CHECK-LABEL: name: test_fptosi_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[FPTOSI]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@ -171,8 +169,7 @@ body: |
; CHECK-LABEL: name: test_fptoui_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@ -187,8 +184,7 @@ body: |
; CHECK-LABEL: name: test_fptosi_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@ -203,8 +199,7 @@ body: |
; CHECK-LABEL: name: test_fptoui_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
View File

@ -107,8 +107,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_freeze_s2
; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
; CHECK: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[COPY]]
; CHECK: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]

834
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
View File

@ -193,647 +193,383 @@ body: |
; CHECK: [[ZEXT55:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT55]], [[C13]](s64)
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C14]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C14]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C14]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C14]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C14]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C3]](s64)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C14]]
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C14]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[COPY10]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C14]]
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C14]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C7]](s64)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY12]], [[COPY13]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C14]]
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C14]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C9]](s64)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[SHL4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[COPY16]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C14]]
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C14]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C11]](s64)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SHL5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[COPY19]]
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C14]]
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C14]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C13]](s64)
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[SHL6]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY21]], [[COPY22]]
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C14]]
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C14]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C1]](s64)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C14]]
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[SHL7]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[COPY24]]
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C14]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C14]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C3]](s64)
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SHL8]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY26]], [[COPY27]]
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C14]]
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C14]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C5]](s64)
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[OR8]](s32)
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[SHL9]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[COPY29]], [[COPY30]]
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C14]]
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C14]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C7]](s64)
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[OR9]](s32)
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[SHL10]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY32]], [[COPY33]]
; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C14]]
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C14]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C9]](s64)
; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[OR10]](s32)
; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[SHL11]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY35]], [[COPY36]]
; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C14]]
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C14]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C11]](s64)
; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[OR11]](s32)
; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[SHL12]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[COPY38]], [[COPY39]]
; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C14]]
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C14]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C13]](s64)
; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[OR12]](s32)
; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[SHL13]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[COPY41]], [[COPY42]]
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C14]]
; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C14]]
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C1]](s64)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C14]]
; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[SHL14]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[COPY44]]
; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C14]]
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C14]]
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C3]](s64)
; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[OR14]](s32)
; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[SHL15]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[COPY46]], [[COPY47]]
; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY48]], [[C14]]
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C14]]
; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C5]](s64)
; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[OR15]](s32)
; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[SHL16]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[COPY49]], [[COPY50]]
; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C14]]
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C14]]
; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C7]](s64)
; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[OR16]](s32)
; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[SHL17]](s32)
; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[COPY52]], [[COPY53]]
; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C14]]
; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C14]]
; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C9]](s64)
; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[OR17]](s32)
; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[SHL18]](s32)
; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[COPY55]], [[COPY56]]
; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C14]]
; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C14]]
; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C11]](s64)
; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[OR18]](s32)
; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[SHL19]](s32)
; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[COPY58]], [[COPY59]]
; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C14]]
; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C14]]
; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C13]](s64)
; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[OR19]](s32)
; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[SHL20]](s32)
; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[COPY61]], [[COPY62]]
; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C14]]
; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C14]]
; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C1]](s64)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C14]]
; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[SHL21]](s32)
; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[COPY64]]
; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY65]], [[C14]]
; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C14]]
; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C3]](s64)
; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[OR21]](s32)
; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[SHL22]](s32)
; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[COPY66]], [[COPY67]]
; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY68]], [[C14]]
; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C14]]
; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C5]](s64)
; CHECK: [[COPY69:%[0-9]+]]:_(s32) = COPY [[OR22]](s32)
; CHECK: [[COPY70:%[0-9]+]]:_(s32) = COPY [[SHL23]](s32)
; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[COPY69]], [[COPY70]]
; CHECK: [[COPY71:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY71]], [[C14]]
; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C14]]
; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C7]](s64)
; CHECK: [[COPY72:%[0-9]+]]:_(s32) = COPY [[OR23]](s32)
; CHECK: [[COPY73:%[0-9]+]]:_(s32) = COPY [[SHL24]](s32)
; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[COPY72]], [[COPY73]]
; CHECK: [[COPY74:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY74]], [[C14]]
; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C14]]
; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C9]](s64)
; CHECK: [[COPY75:%[0-9]+]]:_(s32) = COPY [[OR24]](s32)
; CHECK: [[COPY76:%[0-9]+]]:_(s32) = COPY [[SHL25]](s32)
; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[COPY75]], [[COPY76]]
; CHECK: [[COPY77:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY77]], [[C14]]
; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C14]]
; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C11]](s64)
; CHECK: [[COPY78:%[0-9]+]]:_(s32) = COPY [[OR25]](s32)
; CHECK: [[COPY79:%[0-9]+]]:_(s32) = COPY [[SHL26]](s32)
; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[COPY78]], [[COPY79]]
; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY80]], [[C14]]
; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C14]]
; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C13]](s64)
; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[OR26]](s32)
; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[SHL27]](s32)
; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[COPY81]], [[COPY82]]
; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY83]], [[C14]]
; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C14]]
; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C1]](s64)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C14]]
; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[SHL28]](s32)
; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[COPY84]]
; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY85]], [[C14]]
; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C14]]
; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C3]](s64)
; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[OR28]](s32)
; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[SHL29]](s32)
; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[COPY86]], [[COPY87]]
; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY88]], [[C14]]
; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C14]]
; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C5]](s64)
; CHECK: [[COPY89:%[0-9]+]]:_(s32) = COPY [[OR29]](s32)
; CHECK: [[COPY90:%[0-9]+]]:_(s32) = COPY [[SHL30]](s32)
; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[COPY89]], [[COPY90]]
; CHECK: [[COPY91:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY91]], [[C14]]
; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[LSHR31]], [[C14]]
; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C7]](s64)
; CHECK: [[COPY92:%[0-9]+]]:_(s32) = COPY [[OR30]](s32)
; CHECK: [[COPY93:%[0-9]+]]:_(s32) = COPY [[SHL31]](s32)
; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[COPY92]], [[COPY93]]
; CHECK: [[COPY94:%[0-9]+]]:_(s32) = COPY [[LSHR32]](s32)
; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY94]], [[C14]]
; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[LSHR32]], [[C14]]
; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C9]](s64)
; CHECK: [[COPY95:%[0-9]+]]:_(s32) = COPY [[OR31]](s32)
; CHECK: [[COPY96:%[0-9]+]]:_(s32) = COPY [[SHL32]](s32)
; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[COPY95]], [[COPY96]]
; CHECK: [[COPY97:%[0-9]+]]:_(s32) = COPY [[LSHR33]](s32)
; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY97]], [[C14]]
; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR33]], [[C14]]
; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C11]](s64)
; CHECK: [[COPY98:%[0-9]+]]:_(s32) = COPY [[OR32]](s32)
; CHECK: [[COPY99:%[0-9]+]]:_(s32) = COPY [[SHL33]](s32)
; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[COPY98]], [[COPY99]]
; CHECK: [[COPY100:%[0-9]+]]:_(s32) = COPY [[LSHR34]](s32)
; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY100]], [[C14]]
; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[LSHR34]], [[C14]]
; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C13]](s64)
; CHECK: [[COPY101:%[0-9]+]]:_(s32) = COPY [[OR33]](s32)
; CHECK: [[COPY102:%[0-9]+]]:_(s32) = COPY [[SHL34]](s32)
; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[COPY101]], [[COPY102]]
; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
; CHECK: [[COPY103:%[0-9]+]]:_(s32) = COPY [[LSHR35]](s32)
; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY103]], [[C14]]
; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[LSHR35]], [[C14]]
; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C1]](s64)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C14]]
; CHECK: [[COPY104:%[0-9]+]]:_(s32) = COPY [[SHL35]](s32)
; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[COPY104]]
; CHECK: [[COPY105:%[0-9]+]]:_(s32) = COPY [[LSHR36]](s32)
; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY105]], [[C14]]
; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[SHL35]]
; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[LSHR36]], [[C14]]
; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C3]](s64)
; CHECK: [[COPY106:%[0-9]+]]:_(s32) = COPY [[OR35]](s32)
; CHECK: [[COPY107:%[0-9]+]]:_(s32) = COPY [[SHL36]](s32)
; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[COPY106]], [[COPY107]]
; CHECK: [[COPY108:%[0-9]+]]:_(s32) = COPY [[LSHR37]](s32)
; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY108]], [[C14]]
; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[LSHR37]], [[C14]]
; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C5]](s64)
; CHECK: [[COPY109:%[0-9]+]]:_(s32) = COPY [[OR36]](s32)
; CHECK: [[COPY110:%[0-9]+]]:_(s32) = COPY [[SHL37]](s32)
; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[COPY109]], [[COPY110]]
; CHECK: [[COPY111:%[0-9]+]]:_(s32) = COPY [[LSHR38]](s32)
; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY111]], [[C14]]
; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[LSHR38]], [[C14]]
; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C7]](s64)
; CHECK: [[COPY112:%[0-9]+]]:_(s32) = COPY [[OR37]](s32)
; CHECK: [[COPY113:%[0-9]+]]:_(s32) = COPY [[SHL38]](s32)
; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[COPY112]], [[COPY113]]
; CHECK: [[COPY114:%[0-9]+]]:_(s32) = COPY [[LSHR39]](s32)
; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY114]], [[C14]]
; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[LSHR39]], [[C14]]
; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C9]](s64)
; CHECK: [[COPY115:%[0-9]+]]:_(s32) = COPY [[OR38]](s32)
; CHECK: [[COPY116:%[0-9]+]]:_(s32) = COPY [[SHL39]](s32)
; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[COPY115]], [[COPY116]]
; CHECK: [[COPY117:%[0-9]+]]:_(s32) = COPY [[LSHR40]](s32)
; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY117]], [[C14]]
; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[LSHR40]], [[C14]]
; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C11]](s64)
; CHECK: [[COPY118:%[0-9]+]]:_(s32) = COPY [[OR39]](s32)
; CHECK: [[COPY119:%[0-9]+]]:_(s32) = COPY [[SHL40]](s32)
; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[COPY118]], [[COPY119]]
; CHECK: [[COPY120:%[0-9]+]]:_(s32) = COPY [[LSHR41]](s32)
; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY120]], [[C14]]
; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[LSHR41]], [[C14]]
; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C13]](s64)
; CHECK: [[COPY121:%[0-9]+]]:_(s32) = COPY [[OR40]](s32)
; CHECK: [[COPY122:%[0-9]+]]:_(s32) = COPY [[SHL41]](s32)
; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[COPY121]], [[COPY122]]
; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
; CHECK: [[COPY123:%[0-9]+]]:_(s32) = COPY [[LSHR42]](s32)
; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY123]], [[C14]]
; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[LSHR42]], [[C14]]
; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C1]](s64)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C14]]
; CHECK: [[COPY124:%[0-9]+]]:_(s32) = COPY [[SHL42]](s32)
; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[COPY124]]
; CHECK: [[COPY125:%[0-9]+]]:_(s32) = COPY [[LSHR43]](s32)
; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY125]], [[C14]]
; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[SHL42]]
; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[LSHR43]], [[C14]]
; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C3]](s64)
; CHECK: [[COPY126:%[0-9]+]]:_(s32) = COPY [[OR42]](s32)
; CHECK: [[COPY127:%[0-9]+]]:_(s32) = COPY [[SHL43]](s32)
; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[COPY126]], [[COPY127]]
; CHECK: [[COPY128:%[0-9]+]]:_(s32) = COPY [[LSHR44]](s32)
; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY128]], [[C14]]
; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[LSHR44]], [[C14]]
; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C5]](s64)
; CHECK: [[COPY129:%[0-9]+]]:_(s32) = COPY [[OR43]](s32)
; CHECK: [[COPY130:%[0-9]+]]:_(s32) = COPY [[SHL44]](s32)
; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[COPY129]], [[COPY130]]
; CHECK: [[COPY131:%[0-9]+]]:_(s32) = COPY [[LSHR45]](s32)
; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY131]], [[C14]]
; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[LSHR45]], [[C14]]
; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C7]](s64)
; CHECK: [[COPY132:%[0-9]+]]:_(s32) = COPY [[OR44]](s32)
; CHECK: [[COPY133:%[0-9]+]]:_(s32) = COPY [[SHL45]](s32)
; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[COPY132]], [[COPY133]]
; CHECK: [[COPY134:%[0-9]+]]:_(s32) = COPY [[LSHR46]](s32)
; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY134]], [[C14]]
; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[LSHR46]], [[C14]]
; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C9]](s64)
; CHECK: [[COPY135:%[0-9]+]]:_(s32) = COPY [[OR45]](s32)
; CHECK: [[COPY136:%[0-9]+]]:_(s32) = COPY [[SHL46]](s32)
; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[COPY135]], [[COPY136]]
; CHECK: [[COPY137:%[0-9]+]]:_(s32) = COPY [[LSHR47]](s32)
; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY137]], [[C14]]
; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[LSHR47]], [[C14]]
; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C11]](s64)
; CHECK: [[COPY138:%[0-9]+]]:_(s32) = COPY [[OR46]](s32)
; CHECK: [[COPY139:%[0-9]+]]:_(s32) = COPY [[SHL47]](s32)
; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[COPY138]], [[COPY139]]
; CHECK: [[COPY140:%[0-9]+]]:_(s32) = COPY [[LSHR48]](s32)
; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY140]], [[C14]]
; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[LSHR48]], [[C14]]
; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C13]](s64)
; CHECK: [[COPY141:%[0-9]+]]:_(s32) = COPY [[OR47]](s32)
; CHECK: [[COPY142:%[0-9]+]]:_(s32) = COPY [[SHL48]](s32)
; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[COPY141]], [[COPY142]]
; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
; CHECK: [[COPY143:%[0-9]+]]:_(s32) = COPY [[LSHR49]](s32)
; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY143]], [[C14]]
; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[LSHR49]], [[C14]]
; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C1]](s64)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C14]]
; CHECK: [[COPY144:%[0-9]+]]:_(s32) = COPY [[SHL49]](s32)
; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[COPY144]]
; CHECK: [[COPY145:%[0-9]+]]:_(s32) = COPY [[LSHR50]](s32)
; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY145]], [[C14]]
; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[SHL49]]
; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[LSHR50]], [[C14]]
; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C3]](s64)
; CHECK: [[COPY146:%[0-9]+]]:_(s32) = COPY [[OR49]](s32)
; CHECK: [[COPY147:%[0-9]+]]:_(s32) = COPY [[SHL50]](s32)
; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[COPY146]], [[COPY147]]
; CHECK: [[COPY148:%[0-9]+]]:_(s32) = COPY [[LSHR51]](s32)
; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY148]], [[C14]]
; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[LSHR51]], [[C14]]
; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C5]](s64)
; CHECK: [[COPY149:%[0-9]+]]:_(s32) = COPY [[OR50]](s32)
; CHECK: [[COPY150:%[0-9]+]]:_(s32) = COPY [[SHL51]](s32)
; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[COPY149]], [[COPY150]]
; CHECK: [[COPY151:%[0-9]+]]:_(s32) = COPY [[LSHR52]](s32)
; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY151]], [[C14]]
; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[LSHR52]], [[C14]]
; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C7]](s64)
; CHECK: [[COPY152:%[0-9]+]]:_(s32) = COPY [[OR51]](s32)
; CHECK: [[COPY153:%[0-9]+]]:_(s32) = COPY [[SHL52]](s32)
; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[COPY152]], [[COPY153]]
; CHECK: [[COPY154:%[0-9]+]]:_(s32) = COPY [[LSHR53]](s32)
; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY154]], [[C14]]
; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[LSHR53]], [[C14]]
; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C9]](s64)
; CHECK: [[COPY155:%[0-9]+]]:_(s32) = COPY [[OR52]](s32)
; CHECK: [[COPY156:%[0-9]+]]:_(s32) = COPY [[SHL53]](s32)
; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[COPY155]], [[COPY156]]
; CHECK: [[COPY157:%[0-9]+]]:_(s32) = COPY [[LSHR54]](s32)
; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY157]], [[C14]]
; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[LSHR54]], [[C14]]
; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C11]](s64)
; CHECK: [[COPY158:%[0-9]+]]:_(s32) = COPY [[OR53]](s32)
; CHECK: [[COPY159:%[0-9]+]]:_(s32) = COPY [[SHL54]](s32)
; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[COPY158]], [[COPY159]]
; CHECK: [[COPY160:%[0-9]+]]:_(s32) = COPY [[LSHR55]](s32)
; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY160]], [[C14]]
; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[LSHR55]], [[C14]]
; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C13]](s64)
; CHECK: [[COPY161:%[0-9]+]]:_(s32) = COPY [[OR54]](s32)
; CHECK: [[COPY162:%[0-9]+]]:_(s32) = COPY [[SHL55]](s32)
; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[COPY161]], [[COPY162]]
; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY163:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY163]], [[C1]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s64)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C14]]
; CHECK: [[COPY164:%[0-9]+]]:_(s32) = COPY [[SHL56]](s32)
; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[COPY164]]
; CHECK: [[COPY165:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY165]], [[C3]](s64)
; CHECK: [[COPY166:%[0-9]+]]:_(s32) = COPY [[OR56]](s32)
; CHECK: [[COPY167:%[0-9]+]]:_(s32) = COPY [[SHL57]](s32)
; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[COPY166]], [[COPY167]]
; CHECK: [[COPY168:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY168]], [[C5]](s64)
; CHECK: [[COPY169:%[0-9]+]]:_(s32) = COPY [[OR57]](s32)
; CHECK: [[COPY170:%[0-9]+]]:_(s32) = COPY [[SHL58]](s32)
; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[COPY169]], [[COPY170]]
; CHECK: [[COPY171:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY171]], [[C7]](s64)
; CHECK: [[COPY172:%[0-9]+]]:_(s32) = COPY [[OR58]](s32)
; CHECK: [[COPY173:%[0-9]+]]:_(s32) = COPY [[SHL59]](s32)
; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[COPY172]], [[COPY173]]
; CHECK: [[COPY174:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY174]], [[C9]](s64)
; CHECK: [[COPY175:%[0-9]+]]:_(s32) = COPY [[OR59]](s32)
; CHECK: [[COPY176:%[0-9]+]]:_(s32) = COPY [[SHL60]](s32)
; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[COPY175]], [[COPY176]]
; CHECK: [[COPY177:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY177]], [[C11]](s64)
; CHECK: [[COPY178:%[0-9]+]]:_(s32) = COPY [[OR60]](s32)
; CHECK: [[COPY179:%[0-9]+]]:_(s32) = COPY [[SHL61]](s32)
; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[COPY178]], [[COPY179]]
; CHECK: [[COPY180:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY180]], [[C13]](s64)
; CHECK: [[COPY181:%[0-9]+]]:_(s32) = COPY [[OR61]](s32)
; CHECK: [[COPY182:%[0-9]+]]:_(s32) = COPY [[SHL62]](s32)
; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[COPY181]], [[COPY182]]
; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL56]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C3]](s64)
; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C5]](s64)
; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C7]](s64)
; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C9]](s64)
; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C11]](s64)
; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C13]](s64)
; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[OR61]], [[SHL62]]
; CHECK: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[OR62]](s32)
; CHECK: [[COPY183:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY183]], [[C1]](s64)
; CHECK: [[COPY184:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY185:%[0-9]+]]:_(s32) = COPY [[SHL63]](s32)
; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY184]], [[COPY185]]
; CHECK: [[COPY186:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY186]], [[C3]](s64)
; CHECK: [[COPY187:%[0-9]+]]:_(s32) = COPY [[OR63]](s32)
; CHECK: [[COPY188:%[0-9]+]]:_(s32) = COPY [[SHL64]](s32)
; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[COPY187]], [[COPY188]]
; CHECK: [[COPY189:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY189]], [[C5]](s64)
; CHECK: [[COPY190:%[0-9]+]]:_(s32) = COPY [[OR64]](s32)
; CHECK: [[COPY191:%[0-9]+]]:_(s32) = COPY [[SHL65]](s32)
; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[COPY190]], [[COPY191]]
; CHECK: [[COPY192:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY192]], [[C7]](s64)
; CHECK: [[COPY193:%[0-9]+]]:_(s32) = COPY [[OR65]](s32)
; CHECK: [[COPY194:%[0-9]+]]:_(s32) = COPY [[SHL66]](s32)
; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[COPY193]], [[COPY194]]
; CHECK: [[COPY195:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY195]], [[C9]](s64)
; CHECK: [[COPY196:%[0-9]+]]:_(s32) = COPY [[OR66]](s32)
; CHECK: [[COPY197:%[0-9]+]]:_(s32) = COPY [[SHL67]](s32)
; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[COPY196]], [[COPY197]]
; CHECK: [[COPY198:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY198]], [[C11]](s64)
; CHECK: [[COPY199:%[0-9]+]]:_(s32) = COPY [[OR67]](s32)
; CHECK: [[COPY200:%[0-9]+]]:_(s32) = COPY [[SHL68]](s32)
; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[COPY199]], [[COPY200]]
; CHECK: [[COPY201:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY201]], [[C13]](s64)
; CHECK: [[COPY202:%[0-9]+]]:_(s32) = COPY [[OR68]](s32)
; CHECK: [[COPY203:%[0-9]+]]:_(s32) = COPY [[SHL69]](s32)
; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[COPY202]], [[COPY203]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C1]](s64)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY11]], [[SHL63]]
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C3]](s64)
; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C5]](s64)
; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C7]](s64)
; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C9]](s64)
; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C11]](s64)
; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C13]](s64)
; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
; CHECK: [[TRUNC10:%[0-9]+]]:_(s8) = G_TRUNC [[OR69]](s32)
; CHECK: [[COPY204:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY204]], [[C1]](s64)
; CHECK: [[COPY205:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY206:%[0-9]+]]:_(s32) = COPY [[SHL70]](s32)
; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY205]], [[COPY206]]
; CHECK: [[COPY207:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY207]], [[C3]](s64)
; CHECK: [[COPY208:%[0-9]+]]:_(s32) = COPY [[OR70]](s32)
; CHECK: [[COPY209:%[0-9]+]]:_(s32) = COPY [[SHL71]](s32)
; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[COPY208]], [[COPY209]]
; CHECK: [[COPY210:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY210]], [[C5]](s64)
; CHECK: [[COPY211:%[0-9]+]]:_(s32) = COPY [[OR71]](s32)
; CHECK: [[COPY212:%[0-9]+]]:_(s32) = COPY [[SHL72]](s32)
; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[COPY211]], [[COPY212]]
; CHECK: [[COPY213:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY213]], [[C7]](s64)
; CHECK: [[COPY214:%[0-9]+]]:_(s32) = COPY [[OR72]](s32)
; CHECK: [[COPY215:%[0-9]+]]:_(s32) = COPY [[SHL73]](s32)
; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[COPY214]], [[COPY215]]
; CHECK: [[COPY216:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY216]], [[C9]](s64)
; CHECK: [[COPY217:%[0-9]+]]:_(s32) = COPY [[OR73]](s32)
; CHECK: [[COPY218:%[0-9]+]]:_(s32) = COPY [[SHL74]](s32)
; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[COPY217]], [[COPY218]]
; CHECK: [[COPY219:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY219]], [[C11]](s64)
; CHECK: [[COPY220:%[0-9]+]]:_(s32) = COPY [[OR74]](s32)
; CHECK: [[COPY221:%[0-9]+]]:_(s32) = COPY [[SHL75]](s32)
; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[COPY220]], [[COPY221]]
; CHECK: [[COPY222:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY222]], [[C13]](s64)
; CHECK: [[COPY223:%[0-9]+]]:_(s32) = COPY [[OR75]](s32)
; CHECK: [[COPY224:%[0-9]+]]:_(s32) = COPY [[SHL76]](s32)
; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[COPY223]], [[COPY224]]
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s64)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY19]], [[SHL70]]
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C3]](s64)
; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C5]](s64)
; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C7]](s64)
; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C9]](s64)
; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C11]](s64)
; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C13]](s64)
; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
; CHECK: [[TRUNC11:%[0-9]+]]:_(s8) = G_TRUNC [[OR76]](s32)
; CHECK: [[COPY225:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY225]], [[C1]](s64)
; CHECK: [[COPY226:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY227:%[0-9]+]]:_(s32) = COPY [[SHL77]](s32)
; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY226]], [[COPY227]]
; CHECK: [[COPY228:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY228]], [[C3]](s64)
; CHECK: [[COPY229:%[0-9]+]]:_(s32) = COPY [[OR77]](s32)
; CHECK: [[COPY230:%[0-9]+]]:_(s32) = COPY [[SHL78]](s32)
; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[COPY229]], [[COPY230]]
; CHECK: [[COPY231:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY231]], [[C5]](s64)
; CHECK: [[COPY232:%[0-9]+]]:_(s32) = COPY [[OR78]](s32)
; CHECK: [[COPY233:%[0-9]+]]:_(s32) = COPY [[SHL79]](s32)
; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[COPY232]], [[COPY233]]
; CHECK: [[COPY234:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY234]], [[C7]](s64)
; CHECK: [[COPY235:%[0-9]+]]:_(s32) = COPY [[OR79]](s32)
; CHECK: [[COPY236:%[0-9]+]]:_(s32) = COPY [[SHL80]](s32)
; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[COPY235]], [[COPY236]]
; CHECK: [[COPY237:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY237]], [[C9]](s64)
; CHECK: [[COPY238:%[0-9]+]]:_(s32) = COPY [[OR80]](s32)
; CHECK: [[COPY239:%[0-9]+]]:_(s32) = COPY [[SHL81]](s32)
; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[COPY238]], [[COPY239]]
; CHECK: [[COPY240:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY240]], [[C11]](s64)
; CHECK: [[COPY241:%[0-9]+]]:_(s32) = COPY [[OR81]](s32)
; CHECK: [[COPY242:%[0-9]+]]:_(s32) = COPY [[SHL82]](s32)
; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[COPY241]], [[COPY242]]
; CHECK: [[COPY243:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY243]], [[C13]](s64)
; CHECK: [[COPY244:%[0-9]+]]:_(s32) = COPY [[OR82]](s32)
; CHECK: [[COPY245:%[0-9]+]]:_(s32) = COPY [[SHL83]](s32)
; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[COPY244]], [[COPY245]]
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY26]], [[C1]](s64)
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY27]], [[SHL77]]
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C3]](s64)
; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C5]](s64)
; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C7]](s64)
; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C9]](s64)
; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY32]], [[C11]](s64)
; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C13]](s64)
; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
; CHECK: [[TRUNC12:%[0-9]+]]:_(s8) = G_TRUNC [[OR83]](s32)
; CHECK: [[COPY246:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY246]], [[C1]](s64)
; CHECK: [[COPY247:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY248:%[0-9]+]]:_(s32) = COPY [[SHL84]](s32)
; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY247]], [[COPY248]]
; CHECK: [[COPY249:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY249]], [[C3]](s64)
; CHECK: [[COPY250:%[0-9]+]]:_(s32) = COPY [[OR84]](s32)
; CHECK: [[COPY251:%[0-9]+]]:_(s32) = COPY [[SHL85]](s32)
; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[COPY250]], [[COPY251]]
; CHECK: [[COPY252:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY252]], [[C5]](s64)
; CHECK: [[COPY253:%[0-9]+]]:_(s32) = COPY [[OR85]](s32)
; CHECK: [[COPY254:%[0-9]+]]:_(s32) = COPY [[SHL86]](s32)
; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[COPY253]], [[COPY254]]
; CHECK: [[COPY255:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY255]], [[C7]](s64)
; CHECK: [[COPY256:%[0-9]+]]:_(s32) = COPY [[OR86]](s32)
; CHECK: [[COPY257:%[0-9]+]]:_(s32) = COPY [[SHL87]](s32)
; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[COPY256]], [[COPY257]]
; CHECK: [[COPY258:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY258]], [[C9]](s64)
; CHECK: [[COPY259:%[0-9]+]]:_(s32) = COPY [[OR87]](s32)
; CHECK: [[COPY260:%[0-9]+]]:_(s32) = COPY [[SHL88]](s32)
; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[COPY259]], [[COPY260]]
; CHECK: [[COPY261:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY261]], [[C11]](s64)
; CHECK: [[COPY262:%[0-9]+]]:_(s32) = COPY [[OR88]](s32)
; CHECK: [[COPY263:%[0-9]+]]:_(s32) = COPY [[SHL89]](s32)
; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[COPY262]], [[COPY263]]
; CHECK: [[COPY264:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY264]], [[C13]](s64)
; CHECK: [[COPY265:%[0-9]+]]:_(s32) = COPY [[OR89]](s32)
; CHECK: [[COPY266:%[0-9]+]]:_(s32) = COPY [[SHL90]](s32)
; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[COPY265]], [[COPY266]]
; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY34]], [[C1]](s64)
; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY35]], [[SHL84]]
; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C3]](s64)
; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C5]](s64)
; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C7]](s64)
; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C9]](s64)
; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C11]](s64)
; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C13]](s64)
; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
; CHECK: [[TRUNC13:%[0-9]+]]:_(s8) = G_TRUNC [[OR90]](s32)
; CHECK: [[COPY267:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY267]], [[C1]](s64)
; CHECK: [[COPY268:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY269:%[0-9]+]]:_(s32) = COPY [[SHL91]](s32)
; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY268]], [[COPY269]]
; CHECK: [[COPY270:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY270]], [[C3]](s64)
; CHECK: [[COPY271:%[0-9]+]]:_(s32) = COPY [[OR91]](s32)
; CHECK: [[COPY272:%[0-9]+]]:_(s32) = COPY [[SHL92]](s32)
; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[COPY271]], [[COPY272]]
; CHECK: [[COPY273:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY273]], [[C5]](s64)
; CHECK: [[COPY274:%[0-9]+]]:_(s32) = COPY [[OR92]](s32)
; CHECK: [[COPY275:%[0-9]+]]:_(s32) = COPY [[SHL93]](s32)
; CHECK: [[OR93:%[0-9]+]]:_(s32) = G_OR [[COPY274]], [[COPY275]]
; CHECK: [[COPY276:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY276]], [[C7]](s64)
; CHECK: [[COPY277:%[0-9]+]]:_(s32) = COPY [[OR93]](s32)
; CHECK: [[COPY278:%[0-9]+]]:_(s32) = COPY [[SHL94]](s32)
; CHECK: [[OR94:%[0-9]+]]:_(s32) = G_OR [[COPY277]], [[COPY278]]
; CHECK: [[COPY279:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY279]], [[C9]](s64)
; CHECK: [[COPY280:%[0-9]+]]:_(s32) = COPY [[OR94]](s32)
; CHECK: [[COPY281:%[0-9]+]]:_(s32) = COPY [[SHL95]](s32)
; CHECK: [[OR95:%[0-9]+]]:_(s32) = G_OR [[COPY280]], [[COPY281]]
; CHECK: [[COPY282:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY282]], [[C11]](s64)
; CHECK: [[COPY283:%[0-9]+]]:_(s32) = COPY [[OR95]](s32)
; CHECK: [[COPY284:%[0-9]+]]:_(s32) = COPY [[SHL96]](s32)
; CHECK: [[OR96:%[0-9]+]]:_(s32) = G_OR [[COPY283]], [[COPY284]]
; CHECK: [[COPY285:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY285]], [[C13]](s64)
; CHECK: [[COPY286:%[0-9]+]]:_(s32) = COPY [[OR96]](s32)
; CHECK: [[COPY287:%[0-9]+]]:_(s32) = COPY [[SHL97]](s32)
; CHECK: [[OR97:%[0-9]+]]:_(s32) = G_OR [[COPY286]], [[COPY287]]
; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY42]], [[C1]](s64)
; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY43]], [[SHL91]]
; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C3]](s64)
; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C5]](s64)
; CHECK: [[OR93:%[0-9]+]]:_(s32) = G_OR [[OR92]], [[SHL93]]
; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C7]](s64)
; CHECK: [[OR94:%[0-9]+]]:_(s32) = G_OR [[OR93]], [[SHL94]]
; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C9]](s64)
; CHECK: [[OR95:%[0-9]+]]:_(s32) = G_OR [[OR94]], [[SHL95]]
; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C11]](s64)
; CHECK: [[OR96:%[0-9]+]]:_(s32) = G_OR [[OR95]], [[SHL96]]
; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C13]](s64)
; CHECK: [[OR97:%[0-9]+]]:_(s32) = G_OR [[OR96]], [[SHL97]]
; CHECK: [[TRUNC14:%[0-9]+]]:_(s8) = G_TRUNC [[OR97]](s32)
; CHECK: [[COPY288:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY288]], [[C1]](s64)
; CHECK: [[COPY289:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY290:%[0-9]+]]:_(s32) = COPY [[SHL98]](s32)
; CHECK: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY289]], [[COPY290]]
; CHECK: [[COPY291:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY291]], [[C3]](s64)
; CHECK: [[COPY292:%[0-9]+]]:_(s32) = COPY [[OR98]](s32)
; CHECK: [[COPY293:%[0-9]+]]:_(s32) = COPY [[SHL99]](s32)
; CHECK: [[OR99:%[0-9]+]]:_(s32) = G_OR [[COPY292]], [[COPY293]]
; CHECK: [[COPY294:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY294]], [[C5]](s64)
; CHECK: [[COPY295:%[0-9]+]]:_(s32) = COPY [[OR99]](s32)
; CHECK: [[COPY296:%[0-9]+]]:_(s32) = COPY [[SHL100]](s32)
; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[COPY295]], [[COPY296]]
; CHECK: [[COPY297:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY297]], [[C7]](s64)
; CHECK: [[COPY298:%[0-9]+]]:_(s32) = COPY [[OR100]](s32)
; CHECK: [[COPY299:%[0-9]+]]:_(s32) = COPY [[SHL101]](s32)
; CHECK: [[OR101:%[0-9]+]]:_(s32) = G_OR [[COPY298]], [[COPY299]]
; CHECK: [[COPY300:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY300]], [[C9]](s64)
; CHECK: [[COPY301:%[0-9]+]]:_(s32) = COPY [[OR101]](s32)
; CHECK: [[COPY302:%[0-9]+]]:_(s32) = COPY [[SHL102]](s32)
; CHECK: [[OR102:%[0-9]+]]:_(s32) = G_OR [[COPY301]], [[COPY302]]
; CHECK: [[COPY303:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY303]], [[C11]](s64)
; CHECK: [[COPY304:%[0-9]+]]:_(s32) = COPY [[OR102]](s32)
; CHECK: [[COPY305:%[0-9]+]]:_(s32) = COPY [[SHL103]](s32)
; CHECK: [[OR103:%[0-9]+]]:_(s32) = G_OR [[COPY304]], [[COPY305]]
; CHECK: [[COPY306:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY306]], [[C13]](s64)
; CHECK: [[COPY307:%[0-9]+]]:_(s32) = COPY [[OR103]](s32)
; CHECK: [[COPY308:%[0-9]+]]:_(s32) = COPY [[SHL104]](s32)
; CHECK: [[OR104:%[0-9]+]]:_(s32) = G_OR [[COPY307]], [[COPY308]]
; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY50]], [[C1]](s64)
; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY51]], [[SHL98]]
; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C3]](s64)
; CHECK: [[OR99:%[0-9]+]]:_(s32) = G_OR [[OR98]], [[SHL99]]
; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C5]](s64)
; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[OR99]], [[SHL100]]
; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C7]](s64)
; CHECK: [[OR101:%[0-9]+]]:_(s32) = G_OR [[OR100]], [[SHL101]]
; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C9]](s64)
; CHECK: [[OR102:%[0-9]+]]:_(s32) = G_OR [[OR101]], [[SHL102]]
; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C11]](s64)
; CHECK: [[OR103:%[0-9]+]]:_(s32) = G_OR [[OR102]], [[SHL103]]
; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY57]], [[C13]](s64)
; CHECK: [[OR104:%[0-9]+]]:_(s32) = G_OR [[OR103]], [[SHL104]]
; CHECK: [[TRUNC15:%[0-9]+]]:_(s8) = G_TRUNC [[OR104]](s32)
; CHECK: [[SHL105:%[0-9]+]]:_(s32) = G_SHL [[C15]], [[C1]](s64)
; CHECK: [[COPY309:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY310:%[0-9]+]]:_(s32) = COPY [[SHL105]](s32)
; CHECK: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY309]], [[COPY310]]
; CHECK: [[COPY311:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY311]], [[C3]](s64)
; CHECK: [[COPY312:%[0-9]+]]:_(s32) = COPY [[OR105]](s32)
; CHECK: [[COPY313:%[0-9]+]]:_(s32) = COPY [[SHL106]](s32)
; CHECK: [[OR106:%[0-9]+]]:_(s32) = G_OR [[COPY312]], [[COPY313]]
; CHECK: [[COPY314:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY314]], [[C5]](s64)
; CHECK: [[COPY315:%[0-9]+]]:_(s32) = COPY [[OR106]](s32)
; CHECK: [[COPY316:%[0-9]+]]:_(s32) = COPY [[SHL107]](s32)
; CHECK: [[OR107:%[0-9]+]]:_(s32) = G_OR [[COPY315]], [[COPY316]]
; CHECK: [[COPY317:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY317]], [[C7]](s64)
; CHECK: [[COPY318:%[0-9]+]]:_(s32) = COPY [[OR107]](s32)
; CHECK: [[COPY319:%[0-9]+]]:_(s32) = COPY [[SHL108]](s32)
; CHECK: [[OR108:%[0-9]+]]:_(s32) = G_OR [[COPY318]], [[COPY319]]
; CHECK: [[COPY320:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY320]], [[C9]](s64)
; CHECK: [[COPY321:%[0-9]+]]:_(s32) = COPY [[OR108]](s32)
; CHECK: [[COPY322:%[0-9]+]]:_(s32) = COPY [[SHL109]](s32)
; CHECK: [[OR109:%[0-9]+]]:_(s32) = G_OR [[COPY321]], [[COPY322]]
; CHECK: [[COPY323:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY323]], [[C11]](s64)
; CHECK: [[COPY324:%[0-9]+]]:_(s32) = COPY [[OR109]](s32)
; CHECK: [[COPY325:%[0-9]+]]:_(s32) = COPY [[SHL110]](s32)
; CHECK: [[OR110:%[0-9]+]]:_(s32) = G_OR [[COPY324]], [[COPY325]]
; CHECK: [[COPY326:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY326]], [[C13]](s64)
; CHECK: [[COPY327:%[0-9]+]]:_(s32) = COPY [[OR110]](s32)
; CHECK: [[COPY328:%[0-9]+]]:_(s32) = COPY [[SHL111]](s32)
; CHECK: [[OR111:%[0-9]+]]:_(s32) = G_OR [[COPY327]], [[COPY328]]
; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY58]], [[SHL105]]
; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C3]](s64)
; CHECK: [[OR106:%[0-9]+]]:_(s32) = G_OR [[OR105]], [[SHL106]]
; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C5]](s64)
; CHECK: [[OR107:%[0-9]+]]:_(s32) = G_OR [[OR106]], [[SHL107]]
; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C7]](s64)
; CHECK: [[OR108:%[0-9]+]]:_(s32) = G_OR [[OR107]], [[SHL108]]
; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C9]](s64)
; CHECK: [[OR109:%[0-9]+]]:_(s32) = G_OR [[OR108]], [[SHL109]]
; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C11]](s64)
; CHECK: [[OR110:%[0-9]+]]:_(s32) = G_OR [[OR109]], [[SHL110]]
; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY64]], [[C13]](s64)
; CHECK: [[OR111:%[0-9]+]]:_(s32) = G_OR [[OR110]], [[SHL111]]
; CHECK: [[TRUNC16:%[0-9]+]]:_(s8) = G_TRUNC [[OR111]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC9]](s8), [[TRUNC10]](s8), [[TRUNC11]](s8), [[TRUNC12]](s8), [[TRUNC13]](s8), [[TRUNC14]](s8), [[TRUNC15]](s8), [[TRUNC16]](s8)
; CHECK: $x0 = COPY [[MV]](s64)

15
llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
View File

@ -18,8 +18,7 @@ body: |
; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[FPEXT]](s32), [[FPEXT1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: %ext:_(s32) = G_AND [[FCMP]], [[C1]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = COPY $h0
@ -43,8 +42,7 @@ body: |
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC]](s16), [[FPTRUNC]](s16), [[FPTRUNC]](s16)
; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s16>) = G_FCMP floatpred(uno), %val(<4 x s16>), [[BUILD_VECTOR]]
; CHECK: %ext:_(<4 x s16>) = COPY [[FCMP]](<4 x s16>)
; CHECK: $d0 = COPY %ext(<4 x s16>)
; CHECK: $d0 = COPY [[FCMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%val:_(<4 x s16>) = COPY $d0
%isnan:_(<4 x s1>) = nofpexcept G_ISNAN %val(<4 x s16>)
@ -65,16 +63,13 @@ body: |
; CHECK: %val:_(s16) = COPY $h0
; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %val(s16)
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FPTOSI]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[C1]](s32), [[SEXT_INREG]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: %ext:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: %ext:_(s32) = G_AND [[ICMP]], [[C2]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = COPY $h0

18
llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
View File

@ -151,8 +151,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
@ -169,8 +168,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s32_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0
@ -186,8 +184,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s64_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; CHECK: $x0 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $w0
@ -204,8 +201,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s64_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; CHECK: $x0 = COPY [[UITOFP]](s64)
%0:_(s32) = COPY $w0
@ -281,8 +277,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
@ -299,8 +294,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s32_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0

8
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
View File

@ -65,8 +65,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
; CHECK: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8))
@ -622,10 +621,9 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR3]](s64)
; CHECK: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s64)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
; CHECK: G_STORE [[COPY1]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
; CHECK: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
; CHECK: G_STORE [[LSHR1]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
; CHECK: RET_ReallyLR
%ptr:_(p0) = COPY $x0

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
View File

@ -97,8 +97,7 @@ body: |
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: $w1 = COPY [[COPY3]](s32)
; CHECK: $w1 = COPY [[COPY1]](s32)
; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: BL &memset, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp

7
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
View File

@ -14,8 +14,7 @@ body: |
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C3]](s64)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = G_CONSTANT i64 0
@ -30,6 +29,8 @@ body: |
name: test_merge_s16_s8
body: |
bb.0:
; This isn't legal but we don't support widening the destination type.
; CHECK-LABEL: name: test_merge_s16_s8
; CHECK: %a:_(s32) = COPY $w0
; CHECK: %b:_(s32) = COPY $w1
@ -38,8 +39,6 @@ body: |
; CHECK: %m:_(s16) = G_MERGE_VALUES %a_t(s8), %b_t(s8)
; CHECK: %ext:_(s64) = G_ANYEXT %m(s16)
; CHECK: $x0 = COPY %ext(s64)
; This isn't legal but we don't support widening the destination type.
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w1
%a_t:_(s8) = G_TRUNC %a

60
llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
View File

@ -223,10 +223,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -254,10 +253,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -266,19 +264,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@ -509,10 +506,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -540,10 +536,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -552,19 +547,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@ -795,10 +789,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -826,10 +819,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -838,19 +830,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@ -1081,10 +1072,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -1112,10 +1102,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@ -1124,19 +1113,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF

28
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
View File

@ -34,8 +34,7 @@ body: |
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[ASHR]]
; CHECK: $x0 = COPY [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[ICMP]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_SMULO %0, %1
@ -56,8 +55,7 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]]
; CHECK: $x0 = COPY [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[ICMP]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_UMULO %0, %1
@ -79,8 +77,7 @@ body: |
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %mul, [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s32), [[ASHR]]
; CHECK: $w0 = COPY %mul(s32)
; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
; CHECK: $w0 = COPY %ext_overflow(s32)
; CHECK: $w0 = COPY [[ICMP]](s32)
; CHECK: RET_ReallyLR implicit $w0
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
@ -103,8 +100,7 @@ body: |
; CHECK: %mul:_(s32) = G_MUL %lhs, %rhs
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
; CHECK: $w0 = COPY %mul(s32)
; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
; CHECK: $w0 = COPY %ext_overflow(s32)
; CHECK: $w0 = COPY [[ICMP]](s32)
; CHECK: RET_ReallyLR implicit $w0
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
@ -123,23 +119,17 @@ body: |
; CHECK: %lhs_wide:_(s32) = COPY $w0
; CHECK: %rhs_wide:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %lhs_wide(s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %rhs_wide(s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND %lhs_wide, [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND %rhs_wide, [[C]]
; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[AND1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
; CHECK: %ext_mul:_(s32) = COPY [[MUL]](s32)
; CHECK: $w0 = COPY %ext_mul(s32)
; CHECK: %ext_overflow:_(s32) = COPY [[OR]](s32)
; CHECK: $w0 = COPY %ext_overflow(s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[ICMP1]]
; CHECK: $w0 = COPY [[MUL]](s32)
; CHECK: $w0 = COPY [[OR]](s32)
; CHECK: RET_ReallyLR implicit $w0
%lhs_wide:_(s32) = COPY $w0
%rhs_wide:_(s32) = COPY $w1

10
llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
View File

@ -20,10 +20,9 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s64)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s64)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16), align 4)
; CHECK: G_STORE [[OR]](s32), [[COPY1]](p0) :: (store (s16), align 4)
; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 2, align 2)
; CHECK: $w0 = COPY [[C]](s32)
; CHECK: RET_ReallyLR implicit $w0
@ -50,12 +49,11 @@ body: |
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s64)
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[C1]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s32), align 8)
; CHECK: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s32), align 8)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)

12
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
View File

@ -259,16 +259,14 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: bb.2:
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
; CHECK: $w0 = COPY [[AND1]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
@ -319,13 +317,12 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %7(s16), %bb.1
; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, [[PHI]](s16), %bb.1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: bb.2:
; CHECK: $w0 = COPY [[AND]](s32)
@ -506,12 +503,11 @@ body: |
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
; CHECK: G_BRCOND [[TRUNC3]](s1), %bb.2
; CHECK: G_BR %bb.1
; CHECK: bb.2:
; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[COPY2]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C6]]

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir
View File

@ -7,8 +7,7 @@ body: |
; CHECK-LABEL: name: test_ptr_add_small
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT_INREG]](s64)
; CHECK: $x0 = COPY [[PTR_ADD]](p0)
%0:_(p0) = COPY $x0

147
llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
View File

@ -15,8 +15,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
@ -41,12 +40,9 @@ body: |
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<2 x s32>) = COPY $d0
@ -77,12 +73,9 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<4 x s16>) = COPY $d0
@ -119,18 +112,11 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR6]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<8 x s8>) = COPY $d0
@ -182,30 +168,15 @@ body: |
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[UV14]](s8)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[UV15]](s8)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ANYEXT14]], [[ANYEXT15]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY7]], [[COPY8]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR8]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR9]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[COPY10]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[OR10]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[OR11]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[COPY11]], [[COPY12]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR12]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[OR13]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[OR7]]
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[OR9]]
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[OR11]]
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[OR13]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR14]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR14]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<16 x s8>) = COPY $q0
@ -259,14 +230,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: $w0 = COPY [[COPY7]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[COPY2]]
; CHECK: $w0 = COPY [[OR1]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%2:_(s32) = COPY $w1
@ -299,11 +265,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: $w0 = COPY [[OR2]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<4 x s16>) = COPY $d0
%0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
@ -339,17 +302,10 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
; CHECK: $w0 = COPY [[COPY7]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
; CHECK: $w0 = COPY [[OR6]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<8 x s8>) = COPY $d0
%1:_(s8) = G_VECREDUCE_OR %0(<8 x s8>)
@ -386,17 +342,10 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: $w0 = COPY [[COPY7]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[OR4]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[OR6]]
; CHECK: $w0 = COPY [[OR7]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<16 x s8>) = COPY $q0
%1:_(s8) = G_VECREDUCE_OR %0(<16 x s8>)
@ -436,17 +385,10 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR8]](s32)
; CHECK: $w0 = COPY [[COPY8]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[OR7]]
; CHECK: $w0 = COPY [[OR8]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<16 x s8>) = COPY $q0
%2:_(<16 x s8>) = COPY $q1
@ -477,11 +419,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: $w0 = COPY [[OR2]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<4 x s16>) = COPY $d0
%1:_(s16) = G_VECREDUCE_OR %0(<4 x s16>)
@ -512,11 +451,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
; CHECK: $w0 = COPY [[OR3]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<8 x s16>) = COPY $q0
%1:_(s16) = G_VECREDUCE_OR %0(<8 x s16>)
@ -550,11 +486,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
; CHECK: $w0 = COPY [[OR4]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1

9
llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
View File

@ -50,14 +50,11 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[TRUNC2]]
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC2]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[MUL]]
; CHECK: $w0 = COPY [[SUB]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
View File

@ -85,8 +85,7 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UADDE]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: %add:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)

5
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
View File

@ -75,10 +75,9 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)

110
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
View File

@ -63,28 +63,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
@ -107,28 +99,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
@ -151,28 +135,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 3
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 3
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 3
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 3
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
@ -195,31 +171,20 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: %copy_1:_(s64) = COPY $x0
; CHECK: %copy_2:_(s64) = COPY $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %copy_1(s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 36
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %copy_2(s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 36
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 36
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 36
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68719476735
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[AND]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ASHR]](s64)
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64)
; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY7]], [[COPY8]]
; CHECK: %ext:_(s64) = COPY [[SELECT]](s64)
; CHECK: $x0 = COPY %ext(s64)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[COPY]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
@ -241,22 +206,19 @@ body: |
; CHECK: liveins: $q0, $q1, $x0
; CHECK: %copy_1:_(s128) = COPY $q0
; CHECK: %copy_2:_(s128) = COPY $q1
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %copy_1(s128)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s128), 0
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %copy_2(s128)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s128), 0
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 24
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDO]](s64)

12
llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
View File

@ -16,10 +16,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[BUILD_VECTOR]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY2]], [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
@ -54,10 +53,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[BUILD_VECTOR]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY2]], [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32)
@ -92,10 +90,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[BUILD_VECTOR]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8)
; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[COPY2]], [[BUILD_VECTOR1]](<16 x s8>)
; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<16 x s8>)
; CHECK: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<16 x s8>)
; CHECK: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8)
@ -133,8 +130,7 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT_INREG]](s32), [[C2]](s64)

9
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
View File

@ -14,21 +14,18 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[ASHR]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[LSHR]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC4]], [[C]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC5]], [[AND3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
; CHECK: $w0 = COPY [[SHL]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)

15
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
View File

@ -17,18 +17,15 @@ body: |
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: $w0 = COPY [[SELECT1]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[SELECT2]](s32)
; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
; CHECK: $x0 = COPY [[SELECT4]](s64)
@ -111,8 +108,7 @@ body: |
; CHECK-LABEL: name: testExtOfCopyOfTrunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)
@ -130,8 +126,7 @@ body: |
; CHECK-LABEL: name: testExtOf2CopyOfTrunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
View File

@ -85,8 +85,7 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[USUBE]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: %sub:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)

5
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
View File

@ -75,10 +75,9 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)

110
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
View File

@ -63,28 +63,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
@ -107,28 +99,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
@ -151,28 +135,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 3
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 3
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 3
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 3
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
@ -195,31 +171,20 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: %copy_1:_(s64) = COPY $x0
; CHECK: %copy_2:_(s64) = COPY $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %copy_1(s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 36
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %copy_2(s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 36
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 36
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 36
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68719476735
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[AND]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ASHR]](s64)
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY7]], [[COPY8]]
; CHECK: %ext:_(s64) = COPY [[SELECT]](s64)
; CHECK: $x0 = COPY %ext(s64)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[COPY]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
@ -241,22 +206,19 @@ body: |
; CHECK: liveins: $q0, $q1, $x0
; CHECK: %copy_1:_(s128) = COPY $q0
; CHECK: %copy_2:_(s128) = COPY $q1
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %copy_1(s128)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s128), 0
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %copy_2(s128)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s128), 0
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 24
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBO]](s64)

47
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
View File

@ -70,20 +70,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY6]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
@ -111,20 +106,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY6]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
@ -155,20 +145,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY7]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY2]], [[ADD]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s4) = G_TRUNC %2(s32)

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
View File

@ -86,8 +86,7 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UADDE]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
; CHECK: %add:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)

5
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
View File

@ -76,10 +76,9 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)

45
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
View File

@ -70,20 +70,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY6]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
@ -111,20 +106,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY6]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
@ -152,20 +142,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY [[COPY6]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s4) = G_TRUNC %2(s32)

3
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
View File

@ -86,8 +86,7 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[USUBE]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
; CHECK: %sub:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)

5
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
View File

@ -76,10 +76,9 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)

108
llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
View File

@ -79,8 +79,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -139,8 +138,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -169,8 +167,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -199,8 +196,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -289,8 +285,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ugt), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -349,8 +344,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ugt), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -379,8 +373,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ugt), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -409,8 +402,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ugt), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -499,8 +491,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(uge), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -559,8 +550,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(uge), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -589,8 +579,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(uge), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -619,8 +608,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(uge), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -709,8 +697,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -769,8 +756,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ult), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -799,8 +785,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ult), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -829,8 +814,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ult), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -919,8 +903,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ule), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -979,8 +962,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ule), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -1009,8 +991,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ule), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -1039,8 +1020,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ule), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -1129,8 +1109,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -1189,8 +1168,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sgt), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -1219,8 +1197,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -1249,8 +1226,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sgt), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -1339,8 +1315,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sge), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -1399,8 +1374,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sge), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -1429,8 +1403,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sge), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -1459,8 +1432,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sge), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -1549,8 +1521,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(slt), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -1609,8 +1580,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -1639,8 +1609,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(slt), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -1669,8 +1638,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(slt), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@ -1759,8 +1727,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sle), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@ -1819,8 +1786,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sle), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@ -1849,8 +1815,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sle), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@ -1879,8 +1844,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sle), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1

17
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
View File

@ -19,22 +19,17 @@ body: |
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[DEF1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[DEF1]]
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[C3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C4]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]]
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[OR]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2
; CHECK: bb.2:

6
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
View File

@ -22,11 +22,9 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_legal_const_ext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
; CHECK: $w0 = COPY [[ADD]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s1) = G_CONSTANT i1 2

6
llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
View File

@ -9,11 +9,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: $w0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s1) = G_FCMP floatpred(ogt), %0(s32), %1

6
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
View File

@ -9,8 +9,7 @@ body: |
; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY1]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0
%2:_(<2 x s32>) = G_ANYEXT %1
@ -60,8 +59,7 @@ body: |
; CHECK-LABEL: name: test_anyext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0
%2:_(<3 x s32>) = G_ANYEXT %1

18
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
View File

@ -20,18 +20,14 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[C3]](s32)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[C3]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SHL]](<2 x s16>), [[SHL1]](<2 x s16>)

6
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
View File

@ -418,8 +418,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
@ -440,8 +439,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1

18
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
View File

@ -9,8 +9,7 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
@ -53,15 +52,11 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@ -81,8 +76,7 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16

261
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
View File

@ -14,10 +14,8 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@ -53,10 +51,8 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@ -223,14 +219,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
; CHECK: $vgpr1 = COPY [[SEXT_INREG1]](s32)
; CHECK: $vgpr2 = COPY [[SEXT_INREG2]](s32)
@ -534,14 +526,10 @@ body: |
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND2]](s32), [[AND3]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64), implicit [[MV1]](s64)
@ -587,39 +575,27 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[BITCAST3]](s32), [[LSHR3]](s32)
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST4]](s32), [[LSHR4]](s32), [[BITCAST5]](s32)
; CHECK: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR6]](s32), [[BITCAST7]](s32), [[LSHR7]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>), implicit [[BUILD_VECTOR1]](<3 x s32>), implicit [[BUILD_VECTOR2]](<3 x s32>), implicit [[BUILD_VECTOR3]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@ -646,31 +622,19 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@ -708,57 +672,33 @@ body: |
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 8
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY17]], 8
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 8
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY25]], 8
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG4]], [[C]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG5]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 8
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY29]], 8
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG6]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG7]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG6]], [[C]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG7]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@ -812,109 +752,61 @@ body: |
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 8
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY25]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 8
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY29]], 8
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY32]], 8
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY33]], 8
; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C]]
; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C]]
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG4]], [[C]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG5]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY36]], 8
; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY37]], 8
; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG6]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C]]
; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG7]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C]]
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG6]], [[C]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG7]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY40]](s32)
; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY48]], 8
; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[COPY41]](s32)
; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY49]], 8
; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG8]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY50]], [[C]]
; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG9]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C]]
; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG8]], [[C]]
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG9]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[COPY42]](s32)
; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY52]], 8
; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[COPY43]](s32)
; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY53]], 8
; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG10]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C]]
; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG11]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C]]
; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 8
; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 8
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG10]], [[C]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG11]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[COPY44]](s32)
; CHECK: [[SEXT_INREG12:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY56]], 8
; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[COPY45]](s32)
; CHECK: [[SEXT_INREG13:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY57]], 8
; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG12]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY58]], [[C]]
; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG13]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C]]
; CHECK: [[SEXT_INREG12:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
; CHECK: [[SEXT_INREG13:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG12]], [[C]]
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG13]], [[C]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[COPY46]](s32)
; CHECK: [[SEXT_INREG14:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY60]], 8
; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[COPY47]](s32)
; CHECK: [[SEXT_INREG15:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY61]], 8
; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG14]](s32)
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C]]
; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG15]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C]]
; CHECK: [[SEXT_INREG14:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 8
; CHECK: [[SEXT_INREG15:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY15]], 8
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG14]], [[C]]
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG15]], [[C]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL7]]
; CHECK: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@ -1274,9 +1166,7 @@ body: |
; CHECK-LABEL: name: test_unmerge_values_v2s8_v4s8_trunc_v4s16
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY [[UV]](<2 x s16>)
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY [[UV1]](<2 x s16>)
; CHECK: S_ENDPGM 0, implicit [[COPY1]](<2 x s16>), implicit [[COPY2]](<2 x s16>)
; CHECK: S_ENDPGM 0, implicit [[UV]](<2 x s16>), implicit [[UV1]](<2 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s8>) = G_TRUNC %0
%2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %1
@ -1444,10 +1334,7 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[BITCAST3]](s32), [[LSHR3]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>), %2:_(<3 x s16>) = G_UNMERGE_VALUES %0

29
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
View File

@ -11,8 +11,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0
@ -74,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_zext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[DEF]](s32)
@ -172,8 +170,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
@ -200,10 +197,8 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
@ -232,10 +227,8 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
@ -262,14 +255,10 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)

6
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
View File

@ -9,8 +9,7 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0
@ -27,8 +26,7 @@ body: |
; CHECK-LABEL: name: test_zext_trunc_i64_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0

28
llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
View File

@ -54,12 +54,10 @@ define i16 @halfinsts_add_i16(i16 %arg0) #1 {
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: $vgpr0 = COPY [[ADD]](s32)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
%add = add i16 %arg0, %arg0
ret i16 %add
}
@ -71,18 +69,12 @@ define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: $vgpr0 = COPY [[COPY7]](s32)
; CHECK: $vgpr1 = COPY [[COPY8]](s32)
; CHECK: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
; CHECK: S_SETPC_B64_return [[COPY9]], implicit $vgpr0, implicit $vgpr1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[ADD]](s32)
; CHECK: $vgpr1 = COPY [[ADD1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0, implicit $vgpr1
%add = add <2 x i16> %arg0, %arg0
ret <2 x i16> %add
}

642
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
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File diff suppressed because it is too large Load Diff

620
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
View File

@ -1465,7 +1465,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_movk_i32 s9, 0xff
; GFX6-NEXT: s_mov_b32 s11, 0x80008
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: s_and_b32 s1, s1, s9
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
@ -1473,11 +1474,12 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s0, s0, s11
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_or_b32 s0, s10, s0
; GFX6-NEXT: s_or_b32 s1, s7, s1
; GFX6-NEXT: s_and_b32 s7, s8, s9
; GFX6-NEXT: s_lshr_b32 s8, s2, 16
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX6-NEXT: s_lshr_b32 s10, s2, 24
; GFX6-NEXT: s_and_b32 s13, s2, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, s11
@ -1485,20 +1487,18 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_and_b32 s8, s8, s9
; GFX6-NEXT: s_or_b32 s2, s13, s2
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX6-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX6-NEXT: s_lshr_b32 s12, s3, 8
; GFX6-NEXT: s_and_b32 s3, s3, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_or_b32 s2, s2, s8
; GFX6-NEXT: s_and_b32 s8, s12, s9
; GFX6-NEXT: s_or_b32 s3, s10, s3
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_or_b32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s8, s4, 16
; GFX6-NEXT: s_lshr_b32 s10, s4, 24
@ -1506,101 +1506,105 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s4, s4, s11
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s8, s8, s9
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX6-NEXT: s_or_b32 s4, s13, s4
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_or_b32 s4, s4, s8
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: s_lshr_b32 s12, s5, 8
; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_and_b32 s5, s5, s9
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_and_b32 s8, s12, s9
; GFX6-NEXT: s_or_b32 s5, s10, s5
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_or_b32 s5, s5, s8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: s_and_b32 s6, s6, s9
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX6-NEXT: s_mov_b32 s8, 0xffffff
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
; GFX6-NEXT: s_lshl_b32 s4, s6, 17
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
; GFX6-NEXT: s_or_b32 s0, s4, s0
; GFX6-NEXT: v_and_b32_e32 v2, s8, v3
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
; GFX6-NEXT: v_lshr_b32_e32 v1, s2, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
; GFX6-NEXT: s_lshl_b32 s0, s7, 17
; GFX6-NEXT: s_lshl_b32 s1, s1, 1
; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
; GFX6-NEXT: v_lshr_b32_e32 v0, s3, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshr_b32_e32 v1, s3, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_readfirstlane_b32 s0, v1
; GFX6-NEXT: v_readfirstlane_b32 s1, v0
; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshr_v2i24:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_movk_i32 s10, 0xff
; GFX8-NEXT: s_lshr_b32 s9, s1, 8
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_bfe_u32 s11, 8, 0x100000
; GFX8-NEXT: s_and_b32 s1, s1, s10
; GFX8-NEXT: s_lshr_b32 s6, s0, 8
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s8, s0, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s11
; GFX8-NEXT: s_or_b32 s1, s8, s1
; GFX8-NEXT: s_and_b32 s6, s6, s10
; GFX8-NEXT: s_lshr_b32 s8, s2, 8
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s8, s8, s10
; GFX8-NEXT: s_lshr_b32 s7, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, s10
@ -1608,15 +1612,15 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
; GFX8-NEXT: s_and_b32 s7, s9, s10
; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s9, s2, 16
; GFX8-NEXT: s_lshr_b32 s12, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, s10
; GFX8-NEXT: s_lshl_b32 s8, s8, s11
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s9, s10
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX8-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX8-NEXT: s_lshr_b32 s13, s3, 8
; GFX8-NEXT: s_and_b32 s3, s3, s10
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
@ -1624,110 +1628,115 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshl_b32 s3, s3, s11
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s13, s10
; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s12, s3
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX8-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s3, s3, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 8
; GFX8-NEXT: s_and_b32 s8, s8, s10
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_lshr_b32 s9, s4, 16
; GFX8-NEXT: s_lshr_b32 s12, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, s10
; GFX8-NEXT: s_lshl_b32 s8, s8, s11
; GFX8-NEXT: s_or_b32 s4, s4, s8
; GFX8-NEXT: s_and_b32 s8, s9, s10
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s4, s4, s8
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: s_lshr_b32 s13, s5, 8
; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX8-NEXT: s_and_b32 s5, s5, s10
; GFX8-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX8-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX8-NEXT: s_lshl_b32 s5, s5, s11
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_and_b32 s8, s13, s10
; GFX8-NEXT: s_or_b32 s5, s12, s5
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_or_b32 s5, s5, s8
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX8-NEXT: s_mov_b32 s8, 0xffffff
; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
; GFX8-NEXT: s_lshl_b32 s4, s6, 17
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: v_and_b32_e32 v1, s8, v1
; GFX8-NEXT: v_and_b32_e32 v0, s8, v0
; GFX8-NEXT: s_or_b32 s0, s4, s0
; GFX8-NEXT: v_and_b32_e32 v2, s8, v3
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s2
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
; GFX8-NEXT: s_lshl_b32 s0, s7, 17
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: v_and_b32_e32 v0, v0, v4
; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s3
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v2, 8
; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-NEXT: v_and_b32_e32 v3, s10, v0
; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
; GFX8-NEXT: v_and_b32_e32 v3, s10, v1
; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_readfirstlane_b32 s0, v1
; GFX8-NEXT: v_readfirstlane_b32 s1, v0
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshr_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_movk_i32 s12, 0xff
; GFX9-NEXT: s_lshr_b32 s11, s1, 8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s13, 8, 0x100000
; GFX9-NEXT: s_and_b32 s1, s1, s12
; GFX9-NEXT: s_lshr_b32 s7, s0, 8
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX9-NEXT: s_lshr_b32 s10, s0, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s13
; GFX9-NEXT: s_or_b32 s1, s10, s1
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_and_b32 s7, s7, s12
; GFX9-NEXT: s_lshr_b32 s10, s2, 8
; GFX9-NEXT: s_and_b32 s10, s10, s12
@ -1737,15 +1746,16 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
; GFX9-NEXT: s_and_b32 s9, s11, s12
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s11, s2, 16
; GFX9-NEXT: s_lshr_b32 s14, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, s12
; GFX9-NEXT: s_lshl_b32 s10, s10, s13
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s11, s12
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: s_lshr_b32 s15, s3, 8
; GFX9-NEXT: s_and_b32 s3, s3, s12
; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
@ -1753,18 +1763,15 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshl_b32 s3, s3, s13
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s15, s12
; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s14, s3
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s3, s3, s10
; GFX9-NEXT: s_lshr_b32 s10, s4, 8
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: s_and_b32 s10, s10, s12
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_lshr_b32 s11, s4, 16
; GFX9-NEXT: s_lshr_b32 s14, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, s12
@ -1772,201 +1779,202 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s4, s4, s10
; GFX9-NEXT: s_and_b32 s10, s11, s12
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s4, s4, s10
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_lshr_b32 s15, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, s12
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX9-NEXT: s_lshl_b32 s5, s5, s13
; GFX9-NEXT: s_and_b32 s10, s15, s12
; GFX9-NEXT: s_or_b32 s5, s14, s5
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s5, s5, s10
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX9-NEXT: s_mov_b32 s10, 0xffffff
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
; GFX9-NEXT: v_and_b32_e32 v1, s10, v1
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
; GFX9-NEXT: v_and_b32_e32 v0, s10, v0
; GFX9-NEXT: s_lshl_b32 s4, s7, 17
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: s_or_b32 s0, s4, s0
; GFX9-NEXT: v_and_b32_e32 v3, s10, v3
; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s2
; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: s_bfe_u32 s9, s9, 0x100000
; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
; GFX9-NEXT: v_and_b32_e32 v1, v1, v2
; GFX9-NEXT: s_lshl_b32 s0, s9, 17
; GFX9-NEXT: s_lshl_b32 s1, s1, 1
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: v_and_b32_e32 v3, v3, v2
; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s3
; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
; GFX9-NEXT: s_mov_b32 s6, 8
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX9-NEXT: v_and_b32_e32 v3, s12, v0
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX9-NEXT: v_and_b32_e32 v3, s12, v1
; GFX9-NEXT: s_mov_b32 s8, 16
; GFX9-NEXT: v_and_or_b32 v2, v1, s12, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_and_or_b32 v2, v0, s12, v2
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: v_readfirstlane_b32 s1, v0
; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshr_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX10-NEXT: s_movk_i32 s8, 0xff
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX10-NEXT: s_movk_i32 s9, 0xff
; GFX10-NEXT: s_lshr_b32 s12, s4, 8
; GFX10-NEXT: s_lshr_b32 s13, s4, 16
; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_and_b32 s12, s12, s8
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
; GFX10-NEXT: s_and_b32 s12, s12, s9
; GFX10-NEXT: s_lshr_b32 s14, s4, 24
; GFX10-NEXT: s_and_b32 s4, s4, s8
; GFX10-NEXT: s_and_b32 s4, s4, s9
; GFX10-NEXT: s_lshl_b32 s12, s12, s10
; GFX10-NEXT: s_and_b32 s13, s13, s8
; GFX10-NEXT: s_and_b32 s13, s13, s9
; GFX10-NEXT: s_or_b32 s4, s4, s12
; GFX10-NEXT: s_bfe_u32 s12, s13, 0x100000
; GFX10-NEXT: s_lshr_b32 s15, s5, 8
; GFX10-NEXT: s_and_b32 s5, s5, s8
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: s_lshr_b32 s15, s5, 8
; GFX10-NEXT: s_and_b32 s5, s5, s9
; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: s_lshl_b32 s12, s12, 16
; GFX10-NEXT: s_lshl_b32 s5, s5, s10
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_or_b32 s4, s4, s12
; GFX10-NEXT: s_and_b32 s12, s15, s8
; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
; GFX10-NEXT: s_and_b32 s12, s15, s9
; GFX10-NEXT: s_or_b32 s5, s14, s5
; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
; GFX10-NEXT: s_bfe_u32 s12, s12, 0x100000
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX10-NEXT: s_lshl_b32 s12, s12, 16
; GFX10-NEXT: s_lshr_b32 s11, s1, 8
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: s_or_b32 s5, s5, s12
; GFX10-NEXT: s_and_b32 s1, s1, s8
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX10-NEXT: s_and_b32 s1, s1, s9
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshr_b32 s9, s0, 24
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: s_lshl_b32 s1, s1, s10
; GFX10-NEXT: s_and_b32 s6, s6, s8
; GFX10-NEXT: s_or_b32 s1, s9, s1
; GFX10-NEXT: s_lshr_b32 s9, s2, 8
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_hi_u32 v2, v0, v3
; GFX10-NEXT: s_and_b32 s9, s9, s8
; GFX10-NEXT: s_and_b32 s0, s0, s8
; GFX10-NEXT: s_lshl_b32 s6, s6, s10
; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s7, s8
; GFX10-NEXT: s_and_b32 s7, s11, s8
; GFX10-NEXT: s_and_b32 s6, s6, s9
; GFX10-NEXT: s_or_b32 s1, s8, s1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: s_lshr_b32 s11, s2, 16
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
; GFX10-NEXT: s_and_b32 s8, s8, s9
; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX10-NEXT: s_and_b32 s0, s0, s9
; GFX10-NEXT: s_lshl_b32 s6, s6, s10
; GFX10-NEXT: s_lshr_b32 s13, s2, 24
; GFX10-NEXT: s_and_b32 s2, s2, s8
; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX10-NEXT: s_lshl_b32 s9, s9, s10
; GFX10-NEXT: s_lshr_b32 s12, s3, 8
; GFX10-NEXT: s_or_b32 s2, s2, s9
; GFX10-NEXT: s_and_b32 s9, s11, s8
; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX10-NEXT: s_and_b32 s3, s3, s8
; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s7, s9
; GFX10-NEXT: s_and_b32 s7, s11, s9
; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX10-NEXT: s_bfe_u32 s4, s9, 0x100000
; GFX10-NEXT: s_lshl_b32 s3, s3, s10
; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX10-NEXT: s_lshr_b32 s11, s2, 16
; GFX10-NEXT: s_and_b32 s2, s2, s9
; GFX10-NEXT: s_lshl_b32 s8, s8, s10
; GFX10-NEXT: s_lshr_b32 s12, s3, 8
; GFX10-NEXT: s_or_b32 s2, s2, s8
; GFX10-NEXT: s_and_b32 s8, s11, s9
; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX10-NEXT: s_lshl_b32 s4, s4, 16
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_and_b32 s3, s3, s9
; GFX10-NEXT: s_or_b32 s2, s2, s4
; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
; GFX10-NEXT: s_mov_b32 s4, 0xffffff
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT: s_lshl_b32 s3, s3, s10
; GFX10-NEXT: s_and_b32 s5, s12, s9
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_or_b32 s2, s2, s4
; GFX10-NEXT: s_mov_b32 s4, 0xffffff
; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
; GFX10-NEXT: s_and_b32 s5, s12, s8
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
; GFX10-NEXT: s_or_b32 s3, s13, s3
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_lshl_b32 s5, s5, 16
; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_or_b32 s3, s3, s5
; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX10-NEXT: s_lshl_b32 s5, s6, 17
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v1, s4, v1
; GFX10-NEXT: s_or_b32 s0, s5, s0
; GFX10-NEXT: v_and_b32_e32 v0, s4, v0
; GFX10-NEXT: s_lshl_b32 s5, s6, 17
; GFX10-NEXT: v_and_b32_e32 v3, s4, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v0
; GFX10-NEXT: v_and_b32_e32 v0, v0, v2
; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s2
; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v1
; GFX10-NEXT: v_and_b32_e32 v1, v1, v2
; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_lshl_b32 s2, s7, 17
; GFX10-NEXT: s_lshl_b32 s1, s1, 1
; GFX10-NEXT: v_and_b32_e32 v2, v4, v2
; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s3
; GFX10-NEXT: v_lshl_or_b32 v1, s0, v3, v1
; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX10-NEXT: s_or_b32 s0, s5, s0
; GFX10-NEXT: s_lshl_b32 s1, s1, 1
; GFX10-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX10-NEXT: s_or_b32 s0, s2, s1
; GFX10-NEXT: v_lshl_or_b32 v0, s0, v2, v0
; GFX10-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX10-NEXT: s_mov_b32 s0, 8
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: s_mov_b32 s0, 16
; GFX10-NEXT: v_and_b32_e32 v3, s8, v0
; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
; GFX10-NEXT: v_and_or_b32 v2, v1, s8, v2
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_b32_e32 v3, s9, v1
; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX10-NEXT: v_and_or_b32 v2, v0, s9, v2
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v0
; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@ -1982,40 +1990,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX6-NEXT: v_mul_lo_u32 v9, v8, v7
; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX6-NEXT: v_and_b32_e32 v5, v5, v9
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX6-NEXT: v_and_b32_e32 v3, v3, v9
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX6-NEXT: v_mul_lo_u32 v7, v8, v6
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 23, v4
; GFX6-NEXT: v_and_b32_e32 v8, v8, v9
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v7, v8
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
; GFX6-NEXT: v_and_b32_e32 v7, v7, v9
; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v0
; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX6-NEXT: v_and_b32_e32 v3, v3, v9
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
@ -2037,40 +2047,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX8-NEXT: v_mul_lo_u32 v9, v8, v7
; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX8-NEXT: v_and_b32_e32 v5, v5, v9
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX8-NEXT: v_and_b32_e32 v3, v3, v9
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX8-NEXT: v_mul_lo_u32 v7, v8, v6
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 23, v4
; GFX8-NEXT: v_and_b32_e32 v8, v8, v9
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, v7, v8
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
; GFX8-NEXT: v_and_b32_e32 v7, v7, v9
; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v8, v0
; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6
; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX8-NEXT: v_and_b32_e32 v3, v3, v9
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2
@ -2092,41 +2104,43 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v9, v8, v7
; GFX9-NEXT: v_mul_lo_u32 v8, v8, v6
; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v9
; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX9-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX9-NEXT: v_and_b32_e32 v5, v5, v9
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
; GFX9-NEXT: v_and_b32_e32 v3, v3, v9
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
; GFX9-NEXT: v_mul_hi_u32 v7, v8, v7
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
; GFX9-NEXT: v_and_b32_e32 v7, v7, v9
; GFX9-NEXT: v_and_b32_e32 v6, v6, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@ -2145,30 +2159,32 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_and_b32_e32 v5, v5, v10
; GFX10-NEXT: v_and_b32_e32 v2, v2, v10
; GFX10-NEXT: v_and_b32_e32 v3, v3, v10
; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5

128
llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
View File

@ -16,9 +16,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i16 %s) {
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[DEF]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@ -39,9 +38,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i16 %s) {
; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@ -69,9 +67,7 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i16 %s, i16 %t)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@ -93,9 +89,7 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i16 %s, i16 %t)
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@ -124,12 +118,9 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i16 %s, i16 %t,
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@ -153,12 +144,9 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i16 %s, i16 %t,
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@ -187,9 +175,7 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@ -211,9 +197,7 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@ -242,12 +226,9 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@ -271,12 +252,9 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@ -306,12 +284,9 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i16 %s, i16 %
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@ -335,12 +310,9 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i16 %s, i16 %
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@ -373,9 +345,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10-LABEL: name: store_mip_1d
@ -396,9 +367,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
main_body:
@ -426,9 +396,7 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10-LABEL: name: store_mip_2d
@ -450,9 +418,7 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
main_body:
@ -481,12 +447,9 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@ -510,12 +473,9 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
@ -544,9 +504,7 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10-LABEL: name: store_mip_1darray
@ -568,9 +526,7 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
main_body:
@ -599,12 +555,9 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@ -628,12 +581,9 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
@ -663,12 +613,9 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@ -692,12 +639,9 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0

105
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
View File

@ -79,12 +79,9 @@ body: |
; GFX6-LABEL: name: test_add_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_add_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@ -125,17 +122,11 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -183,17 +174,11 @@ body: |
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY3]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY4]]
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY10]], [[COPY11]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY5]]
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD2]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16)
; GFX8-LABEL: name: test_add_v3s16
@ -220,19 +205,13 @@ body: |
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY6]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[ADD]](<2 x s16>)
@ -283,30 +262,18 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]]
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@ -413,12 +380,9 @@ body: |
; GFX6-LABEL: name: test_add_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_add_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@ -458,27 +422,18 @@ body: |
; GFX6-LABEL: name: test_add_s24
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6: $vgpr0 = COPY [[ADD]](s32)
; GFX8-LABEL: name: test_add_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX8: $vgpr0 = COPY [[ADD]](s32)
; GFX9-LABEL: name: test_add_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32)
; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX9: $vgpr0 = COPY [[ADD]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0

247
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
View File

@ -60,9 +60,7 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@ -100,10 +98,7 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s1)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
@ -186,11 +181,8 @@ body: |
; CHECK-LABEL: name: test_and_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@ -209,11 +201,8 @@ body: |
; CHECK-LABEL: name: test_and_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0
@ -255,11 +244,8 @@ body: |
; CHECK-LABEL: name: test_and_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
@ -278,11 +264,8 @@ body: |
; CHECK-LABEL: name: test_and_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
@ -457,24 +440,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -544,24 +521,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV19]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -630,27 +601,11 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV4]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV5]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV6]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV7]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(<4 x s8>) = G_IMPLICIT_DEF
@ -669,47 +624,15 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV14]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[COPY13]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV15]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[COPY15]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV8]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV9]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV10]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV11]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[UV12]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV13]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[UV14]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[UV15]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32), [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
%0:_(<8 x s8>) = G_IMPLICIT_DEF
%1:_(<8 x s8>) = G_IMPLICIT_DEF
@ -728,89 +651,25 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV16]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV18]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV19]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV20]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV21]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV22]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[COPY13]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV23]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[COPY15]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV16]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV17]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV18]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV19]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[UV20]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV21]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[UV22]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[UV23]]
; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; CHECK: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[UV40]](s32)
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV56]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[COPY25]]
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV41]](s32)
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV57]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[COPY27]]
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[UV42]](s32)
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV58]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[COPY29]]
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV43]](s32)
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[UV59]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[COPY31]]
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[UV44]](s32)
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[UV60]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[COPY33]]
; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[UV45]](s32)
; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[UV61]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[COPY35]]
; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[UV46]](s32)
; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[UV62]](s32)
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[COPY37]]
; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[UV47]](s32)
; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[UV63]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[COPY39]]
; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[AND9]](s32)
; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[AND10]](s32)
; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[AND11]](s32)
; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[AND12]](s32)
; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[AND13]](s32)
; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[AND14]](s32)
; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[AND15]](s32)
; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[COPY40]](s32)
; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[COPY41]](s32)
; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[COPY42]](s32)
; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[COPY43]](s32)
; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[COPY44]](s32)
; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[COPY45]](s32)
; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[COPY46]](s32)
; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[COPY47]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32), [[COPY51]](s32), [[COPY52]](s32), [[COPY53]](s32), [[COPY54]](s32), [[COPY55]](s32), [[COPY56]](s32), [[COPY57]](s32), [[COPY58]](s32), [[COPY59]](s32), [[COPY60]](s32), [[COPY61]](s32), [[COPY62]](s32), [[COPY63]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV40]], [[UV56]]
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV41]], [[UV57]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV42]], [[UV58]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV43]], [[UV59]]
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV44]], [[UV60]]
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[UV45]], [[UV61]]
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[UV46]], [[UV62]]
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[UV47]], [[UV63]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32), [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32), [[AND8]](s32), [[AND9]](s32), [[AND10]](s32), [[AND11]](s32), [[AND12]](s32), [[AND13]](s32), [[AND14]](s32), [[AND15]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
%0:_(<16 x s8>) = G_IMPLICIT_DEF
%1:_(<16 x s8>) = G_IMPLICIT_DEF

30
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
View File

@ -40,8 +40,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@ -56,8 +55,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s24_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@ -101,9 +99,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = G_ANYEXT %0
@ -127,10 +123,7 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0
@ -250,8 +243,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s7_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: S_ENDPGM 0, implicit [[COPY1]](s32)
; CHECK: S_ENDPGM 0, implicit [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@ -266,8 +258,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: S_ENDPGM 0, implicit [[COPY1]](s32)
; CHECK: S_ENDPGM 0, implicit [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@ -633,10 +624,8 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -660,8 +649,7 @@ body: |
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_anyext_s112_to_s128
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128)
; CHECK: S_ENDPGM 0, implicit [[COPY1]](s128)
; CHECK: S_ENDPGM 0, implicit [[COPY]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s112) = G_TRUNC %0
%2:_(s128) = G_ANYEXT %1

228
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
View File

@ -2,7 +2,6 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: test_ashr_s32_s32
@ -95,24 +94,21 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; VI-LABEL: name: test_ashr_s64_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX9-LABEL: name: test_ashr_s64_s16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
@ -131,11 +127,9 @@ body: |
; SI-LABEL: name: test_ashr_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: $vgpr0 = COPY [[COPY3]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@ -170,13 +164,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@ -212,13 +203,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@ -258,19 +246,15 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@ -283,10 +267,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
@ -311,19 +293,15 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s7_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@ -336,10 +314,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
@ -364,35 +340,26 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s24_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; VI: $vgpr0 = COPY [[COPY4]](s32)
; VI: $vgpr0 = COPY [[ASHR]](s32)
; GFX9-LABEL: name: test_ashr_s24_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
@ -412,24 +379,21 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s32_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; VI: $vgpr0 = COPY [[ASHR]](s32)
; GFX9-LABEL: name: test_ashr_s32_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
@ -628,20 +592,14 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -690,17 +648,13 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[UV]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[UV1]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -767,20 +721,14 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
@ -791,24 +739,18 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -853,15 +795,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -894,15 +833,10 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY4]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[BITCAST2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@ -937,37 +871,25 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[AND3]](s32)
; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)

776
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
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30
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
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@ -9,12 +9,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: bitreverse_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s8) = G_BITREVERSE %1
@ -30,12 +28,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: bitreverse_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s16) = G_BITREVERSE %1
@ -51,12 +47,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: bitreverse_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s24) = G_BITREVERSE %1
@ -90,17 +84,13 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[BITCAST]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY2]]
; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[LSHR]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)

174
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
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@ -13,19 +13,12 @@ body: |
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; GFX7: $vgpr0 = COPY [[COPY7]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; GFX7: $vgpr0 = COPY [[OR]](s32)
; GFX8-LABEL: name: bswap_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
@ -50,14 +43,12 @@ body: |
; GFX7-LABEL: name: bswap_s16
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@ -86,27 +77,18 @@ body: |
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; GFX7: $vgpr0 = COPY [[COPY7]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; GFX7: $vgpr0 = COPY [[OR]](s32)
; GFX8-LABEL: name: bswap_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; GFX8: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX8: $vgpr0 = COPY [[COPY2]](s32)
; GFX8: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s24) = G_BSWAP %1
@ -145,24 +127,20 @@ body: |
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C1]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY2]](s32)
; GFX7: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; GFX7: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
; GFX7: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@ -191,34 +169,28 @@ body: |
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY4]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY3]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[COPY6]](s32)
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY4]](s32)
; GFX7: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; GFX7: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY8]](s32)
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
; GFX7: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX7: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
; GFX7: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[COPY10]](s32)
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY6]](s32)
; GFX7: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; GFX7: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY12]](s32)
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY7]](s32)
; GFX7: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@ -232,16 +204,13 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@ -253,12 +222,9 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[BSWAP1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX8: $vgpr0 = COPY [[COPY6]](s32)
; GFX8: $vgpr1 = COPY [[COPY7]](s32)
; GFX8: $vgpr2 = COPY [[COPY8]](s32)
; GFX8: $vgpr0 = COPY [[BITCAST2]](s32)
; GFX8: $vgpr1 = COPY [[LSHR]](s32)
; GFX8: $vgpr2 = COPY [[BITCAST3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@ -292,44 +258,36 @@ body: |
; GFX7: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C1]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY2]](s32)
; GFX7: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; GFX7: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX7: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; GFX7: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX7: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
; GFX7: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[COPY8]](s32)
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[COPY4]](s32)
; GFX7: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; GFX7: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; GFX7: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY10]](s32)
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
; GFX7: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; GFX7: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; GFX7: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
; GFX7: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX7: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[COPY12]](s32)
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[COPY6]](s32)
; GFX7: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; GFX7: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C2]]
; GFX7: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY14]](s32)
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX7: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; GFX7: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; GFX7: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC7]], [[TRUNC6]]
; GFX7: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)

300
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
View File

@ -14,10 +14,8 @@ body: |
; GFX78: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX78: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@ -26,9 +24,7 @@ body: |
; GFX9-LABEL: name: build_vector_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@ -51,25 +47,19 @@ body: |
; GFX78: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX78: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX78: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -81,15 +71,9 @@ body: |
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
%0:_(s32) = COPY $vgpr0
@ -115,18 +99,14 @@ body: |
; GFX78: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX78: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@ -137,12 +117,8 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
%0:_(s32) = COPY $vgpr0
@ -172,39 +148,29 @@ body: |
; GFX78: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX78: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX78: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; GFX78: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX78: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; GFX78: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX78: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX78: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX78: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@ -218,21 +184,11 @@ body: |
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<10 x s16>)
%0:_(s32) = COPY $vgpr0
@ -267,53 +223,39 @@ body: |
; GFX78: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX78: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX78: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; GFX78: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX78: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; GFX78: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX78: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX78: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; GFX78: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX78: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX78: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; GFX78: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
; GFX78: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; GFX78: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX78: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; GFX78: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
; GFX78: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; GFX78: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; GFX78: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
@ -329,27 +271,13 @@ body: |
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<14 x s16>)
%0:_(s32) = COPY $vgpr0
@ -387,32 +315,24 @@ body: |
; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; GFX78: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX78: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; GFX78: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX78: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; GFX78: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; GFX78: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@ -427,18 +347,10 @@ body: |
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<8 x s16>)
%0:_(s32) = COPY $vgpr0
@ -485,60 +397,44 @@ body: |
; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
; GFX78: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX78: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
; GFX78: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX78: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
; GFX78: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX78: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
; GFX78: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C]]
; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX78: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C]]
; GFX78: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C]]
; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX78: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C]]
; GFX78: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C]]
; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; GFX78: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX78: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX78: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; GFX78: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
; GFX78: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; GFX78: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; GFX78: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX78: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; GFX78: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C]]
; GFX78: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C]]
; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
; GFX78: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; GFX78: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; GFX78: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; GFX78: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX78: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
; GFX78: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
; GFX78: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
; GFX78: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; GFX78: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; GFX78: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C1]](s32)
; GFX78: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL7]]
; GFX78: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@ -561,30 +457,14 @@ body: |
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[COPY27]](s32)
; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY28]](s32), [[COPY29]](s32)
; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY30]](s32), [[COPY31]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<16 x s16>)
%0:_(s32) = COPY $vgpr0

18
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
View File

@ -233,24 +233,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)

6
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
View File

@ -60,8 +60,7 @@ body: |
; CHECK-LABEL: name: test_constant_s7
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[C]](s32)
%0:_(s7) = G_CONSTANT i7 5
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
@ -74,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_constant_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[C]](s32)
%0:_(s8) = G_CONSTANT i8 5
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1

38
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
View File

@ -57,8 +57,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTLZ_ZERO_UNDEF]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTLZ_ZERO_UNDEF]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTLZ_ZERO_UNDEF %0
@ -75,14 +74,12 @@ body: |
; CHECK-LABEL: name: ctlz_zero_undef_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@ -139,20 +136,16 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND1]](s32)
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF1]], [[C]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -172,14 +165,12 @@ body: |
; CHECK-LABEL: name: ctlz_zero_undef_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@ -198,8 +189,7 @@ body: |
; CHECK-LABEL: name: ctlz_zero_undef_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31

38
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
View File

@ -65,8 +65,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTLZ %0
@ -83,16 +82,14 @@ body: |
; CHECK-LABEL: name: ctlz_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@ -155,23 +152,19 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C2]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND1]](s32)
; CHECK: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C2]]
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMIN1]], [[C]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -191,16 +184,14 @@ body: |
; CHECK-LABEL: name: ctlz_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@ -219,8 +210,7 @@ body: |
; CHECK-LABEL: name: ctlz_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]

45
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
View File

@ -57,8 +57,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTPOP]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTPOP %0
@ -75,12 +74,10 @@ body: |
; CHECK-LABEL: name: ctpop_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@ -137,18 +134,14 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTPOP1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -168,12 +161,10 @@ body: |
; CHECK-LABEL: name: ctpop_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@ -192,16 +183,12 @@ body: |
; CHECK-LABEL: name: ctpop_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C1]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTPOP %1

45
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
View File

@ -57,8 +57,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTTZ_ZERO_UNDEF]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTTZ_ZERO_UNDEF %0
@ -74,12 +73,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: cttz_zero_undef_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@ -135,17 +132,13 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[BITCAST]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[LSHR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@ -164,12 +157,10 @@ body: |
; CHECK-LABEL: name: cttz_zero_undef_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@ -187,15 +178,11 @@ body: |
; CHECK-LABEL: name: cttz_zero_undef_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s64)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ_ZERO_UNDEF %1

45
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
View File

@ -65,8 +65,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTTZ %0
@ -82,14 +81,12 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: cttz_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@ -151,20 +148,16 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[BITCAST]], [[C1]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[C1]]
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -183,14 +176,12 @@ body: |
; CHECK-LABEL: name: cttz_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@ -208,17 +199,13 @@ body: |
; CHECK-LABEL: name: cttz_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C1]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ %1

442
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
View File

@ -205,14 +205,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<2 x s8>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
@ -231,8 +229,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[DEF]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@ -248,14 +245,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
@ -272,14 +267,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s1) = G_CONSTANT i1 false
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
@ -303,16 +296,11 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[COPY1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@ -338,16 +326,11 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@ -374,16 +357,11 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 32
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@ -418,22 +396,13 @@ body: |
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C6]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 4
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 4
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 4
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 4
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 4
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 4
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 4
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 4
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY10]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@ -453,15 +422,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s8_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(<3 x s8>) = G_TRUNC %0
@ -487,26 +454,21 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[SHL3]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(<4 x s8>) = G_BITCAST %0
@ -532,23 +494,18 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY5]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 0
@ -573,23 +530,18 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY5]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 1
@ -614,23 +566,18 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY5]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 2
@ -655,23 +602,18 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY5]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 3
@ -706,15 +648,13 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
@ -722,14 +662,12 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@ -744,8 +682,7 @@ body: |
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[EVEC]], [[SHL6]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr0 = COPY [[LSHR7]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(<8 x s8>) = G_BITCAST %0
@ -774,15 +711,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C2]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C2]](s16)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@ -790,10 +725,9 @@ body: |
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 0
%2:_(<8 x s8>) = G_BITCAST %0
@ -820,15 +754,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@ -836,10 +768,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 1
%2:_(<8 x s8>) = G_BITCAST %0
@ -866,15 +797,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@ -882,10 +811,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C4]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C4]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 3
%2:_(<8 x s8>) = G_BITCAST %0
@ -912,15 +840,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@ -928,11 +854,10 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C5]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C5]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 4
%2:_(<8 x s8>) = G_BITCAST %0
@ -959,15 +884,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@ -975,10 +898,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 5
%2:_(<8 x s8>) = G_BITCAST %0
@ -1005,15 +927,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@ -1021,10 +941,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C4]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C4]](s32)
; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 7
%2:_(<8 x s8>) = G_BITCAST %0
@ -1049,8 +968,7 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[SHL]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@ -1070,8 +988,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@ -1091,8 +1008,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@ -1112,8 +1028,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 2
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@ -1131,15 +1046,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(<3 x s16>) = G_TRUNC %0
@ -1157,15 +1070,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx0_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 0
%2:_(<3 x s16>) = G_TRUNC %0
@ -1183,15 +1094,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx1_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 32
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 1
%2:_(<3 x s16>) = G_TRUNC %0
@ -1209,15 +1118,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx2_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 2
%2:_(<3 x s16>) = G_TRUNC %0
@ -1236,8 +1143,7 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx3_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[DEF]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 3
%2:_(<3 x s16>) = G_TRUNC %0
@ -1264,8 +1170,7 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EVEC]], [[SHL]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr0 = COPY [[LSHR1]](s32)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@ -1995,138 +1900,105 @@ body: |
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C29]](s32)
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C30]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C7]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C8]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C9]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C10]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C11]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C12]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C13]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C]]
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C14]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C]]
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C15]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C]]
; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C16]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C]]
; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C17]](s32)
; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C]]
; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C]]
; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C18]](s32)
; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C]]
; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C]]
; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C19]](s32)
; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C]]
; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C]]
; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C20]](s32)
; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C]]
; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C]]
; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C21]](s32)
; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C]]
; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C]]
; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C22]](s32)
; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C]]
; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C23]](s32)
; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C]]
; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C24]](s32)
; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C]]
; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C]]
; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C25]](s32)
; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C]]
; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C]]
; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C26]](s32)
; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C]]
; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C27]](s32)
; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C]]
; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C28]](s32)
; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C]]
; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C]]
; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C29]](s32)
; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C]]
; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C]]
; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C30]](s32)
; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C30]]
; CHECK: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C31]](s32)
; CHECK: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[OR30]], [[SHL31]](s32)
; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: $vgpr0 = COPY [[COPY34]](s32)
; CHECK: $vgpr0 = COPY [[LSHR31]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(<32 x s1>) = G_BITCAST %0
@ -2158,46 +2030,34 @@ body: |
; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@ -2208,8 +2068,7 @@ body: |
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C5]](s32)
; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[EVEC]], [[SHL9]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; CHECK: $vgpr0 = COPY [[COPY14]](s32)
; CHECK: $vgpr0 = COPY [[LSHR10]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<12 x s8>) = G_BITCAST %0
%2:_(s32) = COPY $vgpr3
@ -2233,19 +2092,12 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY8]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0

63
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
View File

@ -72,8 +72,7 @@ body: |
; CHECK-LABEL: name: test_extract_s32_s48_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
@ -526,16 +525,13 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@ -615,8 +611,7 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 0
@ -669,8 +664,7 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@ -686,8 +680,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@ -703,8 +696,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@ -720,8 +712,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@ -737,8 +728,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@ -753,8 +743,7 @@ body: |
; CHECK-LABEL: name: test_extract_s8_p3_offset0
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[PTRTOINT]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@ -771,8 +760,7 @@ body: |
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@ -786,8 +774,7 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s1_s8_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s1) = G_EXTRACT %1, 0
@ -961,8 +948,7 @@ body: |
; CHECK-LABEL: name: extract_s16_v2s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@ -980,8 +966,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@ -999,8 +984,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@ -1018,8 +1002,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@ -1034,8 +1017,7 @@ body: |
; CHECK-LABEL: name: extract_s16_s32_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@ -1052,8 +1034,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@ -1070,8 +1051,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@ -1088,8 +1068,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1

73
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
View File

@ -218,15 +218,12 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@ -242,24 +239,18 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; SI: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@ -275,15 +266,12 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@ -299,24 +287,18 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; VI: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@ -331,12 +313,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[DEF2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF2]](s32)
; GFX9: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[FABS:%[0-9]+]]:_(<2 x s16>) = G_FABS [[BUILD_VECTOR_TRUNC]]
; GFX9: [[FABS1:%[0-9]+]]:_(<2 x s16>) = G_FABS [[BUILD_VECTOR_TRUNC1]]
@ -348,15 +327,9 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF

44
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
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@ -389,15 +389,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -442,15 +439,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -465,23 +459,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[DEF]](s32)
; GFX9: [[FADD:%[0-9]+]]:_(<2 x s16>) = G_FADD [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[FADD1:%[0-9]+]]:_(<2 x s16>) = G_FADD [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@ -495,15 +483,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2

12
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
View File

@ -280,12 +280,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[DEF2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF2]](s32)
; GFX9: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[BUILD_VECTOR_TRUNC]]
; GFX9: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[BUILD_VECTOR_TRUNC1]]
@ -293,10 +290,7 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FCANONICALIZE1]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST2]](s32), [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_FCANONICALIZE %0

38
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
View File

@ -117,9 +117,7 @@ body: |
; GFX7: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_fcmp_v2s32
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -129,9 +127,7 @@ body: |
; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fcmp_v2s32
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -164,9 +160,7 @@ body: |
; GFX7: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_fcmp_v2s32_flags
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -176,9 +170,7 @@ body: |
; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fcmp_v2s32_flags
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@ -215,10 +207,7 @@ body: |
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX8-LABEL: name: test_fcmp_v3s32
; GFX8: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
@ -231,10 +220,7 @@ body: |
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX9-LABEL: name: test_fcmp_v3s32
; GFX9: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
@ -277,11 +263,7 @@ body: |
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
; GFX7: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP3]](s1)
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX8-LABEL: name: test_fcmp_v4s32
; GFX8: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@ -297,11 +279,7 @@ body: |
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
; GFX8: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP3]](s1)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX9-LABEL: name: test_fcmp_v4s32
; GFX9: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF

18
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
View File

@ -299,8 +299,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
@ -313,8 +312,7 @@ body: |
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
@ -327,8 +325,7 @@ body: |
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
@ -806,8 +803,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
@ -820,8 +816,7 @@ body: |
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
@ -834,8 +829,7 @@ body: |
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]

51
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
View File

@ -453,15 +453,12 @@ body: |
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -515,15 +512,12 @@ body: |
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMA2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -539,33 +533,24 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[DEF]](s32)
; GFX9: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<6 x s16>)
; GFX9: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[DEF]](s32)
; GFX9: [[FMA:%[0-9]+]]:_(<2 x s16>) = G_FMA [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]], [[BUILD_VECTOR_TRUNC4]]
; GFX9: [[FMA1:%[0-9]+]]:_(<2 x s16>) = G_FMA [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC5]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@ -579,15 +564,9 @@ body: |
; GFX9: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX9: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[BITCAST8]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR8]](s32), [[BITCAST9]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>), [[BUILD_VECTOR_TRUNC8]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2

30
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
View File

@ -438,15 +438,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -497,15 +494,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMAXNUM_IEEE2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -538,15 +532,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2

30
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
View File

@ -438,15 +438,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -497,15 +494,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMINNUM_IEEE2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -538,15 +532,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2

45
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
View File

@ -2,7 +2,6 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: test_fmul_s32
@ -376,15 +375,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -429,15 +425,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMUL2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -452,23 +445,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[DEF]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[DEF]](s32)
; GFX9: [[FMUL:%[0-9]+]]:_(<2 x s16>) = G_FMUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[FMUL1:%[0-9]+]]:_(<2 x s16>) = G_FMUL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@ -482,15 +469,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2

52
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
View File

@ -216,15 +216,12 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@ -236,12 +233,9 @@ body: |
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND3]](s32), [[AND4]](s32), [[AND5]](s32)
; SI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; VI-LABEL: name: test_fneg_v3s16
@ -254,15 +248,12 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@ -274,12 +265,9 @@ body: |
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; VI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND3]](s32), [[AND4]](s32), [[AND5]](s32)
; VI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX9-LABEL: name: test_fneg_v3s16
@ -291,12 +279,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[DEF2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF2]](s32)
; GFX9: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[FNEG:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[BUILD_VECTOR_TRUNC]]
; GFX9: [[FNEG1:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[BUILD_VECTOR_TRUNC1]]
@ -305,12 +290,9 @@ body: |
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF

63
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
View File

@ -101,8 +101,7 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
@ -125,13 +124,11 @@ body: |
; SI-LABEL: name: test_fptosi_s32_to_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s32_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@ -147,13 +144,11 @@ body: |
; SI-LABEL: name: test_fptosi_s64_to_s16
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s64_to_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@ -608,14 +603,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s15) = G_FPTOSI %1
@ -634,14 +627,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s17) = G_FPTOSI %1
@ -675,8 +666,7 @@ body: |
; SI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[ASHR]]
; SI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
; SI: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
; SI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
; SI: $vgpr0_vgpr1 = COPY [[MV2]](s64)
; VI-LABEL: name: test_fptosi_s32_to_s33
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
@ -697,8 +687,7 @@ body: |
; VI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[ASHR]]
; VI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
; VI: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
; VI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
; VI: $vgpr0_vgpr1 = COPY [[MV2]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s33) = G_FPTOSI %0
%2:_(s64) = G_ANYEXT %1
@ -716,14 +705,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s7) = G_FPTOSI %1
@ -742,14 +729,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_FPTOSI %1
@ -768,14 +753,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s9
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s9) = G_FPTOSI %1
@ -792,13 +775,11 @@ body: |
; SI-LABEL: name: test_fptosi_s32_to_s15
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s32_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s15) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@ -814,13 +795,11 @@ body: |
; SI-LABEL: name: test_fptosi_s32_to_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s32_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s17) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1

63
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
View File

@ -101,8 +101,7 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
@ -125,13 +124,11 @@ body: |
; SI-LABEL: name: test_fptoui_s32_to_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s32_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@ -147,13 +144,11 @@ body: |
; SI-LABEL: name: test_fptoui_s64_to_s16
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s64_to_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@ -556,14 +551,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s15) = G_FPTOUI %1
@ -582,14 +575,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s17) = G_FPTOUI %1
@ -614,8 +605,7 @@ body: |
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s32)
; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s32)
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOUI]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; SI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
; SI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; VI-LABEL: name: test_fptoui_s32_to_s33
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
@ -627,8 +617,7 @@ body: |
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s32)
; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s32)
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOUI]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; VI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s33) = G_FPTOUI %0
%2:_(s64) = G_ANYEXT %1
@ -646,14 +635,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s7) = G_FPTOUI %1
@ -672,14 +659,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_FPTOUI %1
@ -698,14 +683,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s9
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s9) = G_FPTOUI %1
@ -722,13 +705,11 @@ body: |
; SI-LABEL: name: test_fptoui_s32_to_s15
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s32_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s15) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@ -744,13 +725,11 @@ body: |
; SI-LABEL: name: test_fptoui_s32_to_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32)
; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s32_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
; VI: $vgpr0 = COPY [[COPY1]](s32)
; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s17) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1

22
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
View File

@ -70,9 +70,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST1]](s32), [[LSHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_FPTRUNC %0
@ -151,8 +149,7 @@ body: |
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[OR7]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTRUNC %0
%2:_(s32) = G_ANYEXT %1
@ -274,10 +271,8 @@ body: |
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C21]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR15]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C21]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR7]], [[C21]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR15]], [[C21]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C19]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL4]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
@ -358,8 +353,7 @@ body: |
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[OR7]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTRUNC %0
%2:_(s32) = afn G_ANYEXT %1
@ -481,10 +475,8 @@ body: |
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C21]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR15]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C21]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR7]], [[C21]]
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR15]], [[C21]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C19]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL4]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)

67
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
View File

@ -27,10 +27,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FREEZE]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
; CHECK: $vgpr0 = COPY [[FREEZE]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
%2:_(s7) = G_FREEZE %1
@ -45,10 +43,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FREEZE]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
; CHECK: $vgpr0 = COPY [[FREEZE]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s8) = G_FREEZE %1
@ -95,10 +91,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[FREEZE]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
; CHECK: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
; CHECK: $vgpr0_vgpr1 = COPY [[FREEZE]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s48) = G_FREEZE %1
@ -474,12 +468,9 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[COPY4:%[0-9]+]]:_(<2 x s32>) = COPY [[FREEZE]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[FREEZE]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
@ -505,13 +496,9 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<3 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[COPY5:%[0-9]+]]:_(<3 x s32>) = COPY [[FREEZE]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY5]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[FREEZE]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
@ -527,10 +514,8 @@ body: |
; CHECK-LABEL: name: test_freeze_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[FREEZE]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY2]](<2 x s32>)
; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[COPY]]
; CHECK: $vgpr0_vgpr1 = COPY [[FREEZE]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s8>) = G_FREEZE %1
@ -601,10 +586,7 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR2]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0
@ -656,12 +638,7 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32), [[LSHR1]](s32), [[BITCAST2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[BUILD_VECTOR3]](<5 x s32>)
%0:_(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
%1:_(<5 x s16>) = G_TRUNC %0
@ -723,22 +700,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: S_ENDPGM 0, implicit [[COPY12]](s32), implicit [[COPY13]](s32), implicit [[COPY14]](s32), implicit [[COPY15]](s32)
; CHECK: S_ENDPGM 0, implicit [[UV]](s32), implicit [[UV1]](s32), implicit [[UV2]](s32), implicit [[UV3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2

473
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
View File

@ -136,17 +136,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ZEXT]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC2]]
@ -226,17 +223,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
@ -244,16 +238,13 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC4]], [[TRUNC5]]
@ -406,117 +397,80 @@ body: |
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
; SI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[AND2]](s32)
; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[COPY16]]
; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; SI: $vgpr0 = COPY [[COPY17]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY3]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_fshl_s8_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; VI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
; VI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; VI: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[TRUNC3]](s16)
; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; VI: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR]](s16)
; VI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C4]]
; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND5]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND6]], [[TRUNC4]](s16)
; VI: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[TRUNC3]](s16)
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
; VI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C4]]
; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[TRUNC4]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; VI: $vgpr0 = COPY [[COPY13]](s32)
; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_fshl_s8_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[TRUNC3]](s16)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; GFX9: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR]](s16)
; GFX9: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C4]]
; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND5]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND6]], [[TRUNC4]](s16)
; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[TRUNC3]](s16)
; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C4]]
; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[TRUNC4]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; GFX9: $vgpr0 = COPY [[COPY13]](s32)
; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@ -541,52 +495,39 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; SI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; SI: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; SI: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; SI: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; SI: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; SI: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; SI: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
; SI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
; SI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; SI: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; SI: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; SI: $vgpr0 = COPY [[COPY15]](s32)
; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_fshl_s24_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@ -594,52 +535,39 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; VI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; VI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; VI: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; VI: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; VI: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; VI: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; VI: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; VI: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
; VI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
; VI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; VI: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; VI: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; VI: $vgpr0 = COPY [[COPY15]](s32)
; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_fshl_s24_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@ -647,52 +575,39 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX9: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX9: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX9: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; GFX9: $vgpr0 = COPY [[COPY15]](s32)
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@ -740,17 +655,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC4]]
@ -758,16 +670,13 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[ZEXT2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY10]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY6]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC6]]
@ -775,16 +684,13 @@ body: |
; SI: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
; SI: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[ZEXT4]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY14]](s32)
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY7]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC7]], [[TRUNC8]]
@ -802,15 +708,12 @@ body: |
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL3]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C4]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT8]], [[SHL4]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]]
; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]]
; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND13]], [[SHL5]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@ -886,15 +789,12 @@ body: |
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C4]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@ -914,60 +814,51 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[COPY6]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[COPY7]](s32)
; GFX9: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[COPY4]](<2 x s16>)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[COPY5]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[DEF1]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[C1]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC4]], [[BUILD_VECTOR_TRUNC6]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[C2]](s32)
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[C2]](s32)
; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC4]], [[BUILD_VECTOR_TRUNC7]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[XOR]], [[BUILD_VECTOR_TRUNC6]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[C3]](s32)
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[C3]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[AND]](<2 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[BUILD_VECTOR_TRUNC2]], [[BUILD_VECTOR_TRUNC8]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[LSHR6]], [[AND1]](<2 x s16>)
; GFX9: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[SHL]], [[LSHR7]]
; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC5]], [[BUILD_VECTOR_TRUNC9]]
; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC5]], [[BUILD_VECTOR_TRUNC10]]
; GFX9: [[AND3:%[0-9]+]]:_(<2 x s16>) = G_AND [[XOR1]], [[BUILD_VECTOR_TRUNC9]]
; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[AND2]](<2 x s16>)
; GFX9: [[LSHR8:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC11]](<2 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[LSHR8]], [[AND3]](<2 x s16>)
@ -983,15 +874,9 @@ body: |
; GFX9: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX9: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[COPY27]](s32)
; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY28]](s32), [[COPY29]](s32)
; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY30]](s32), [[COPY31]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR10]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[BITCAST8]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR12]](s32), [[BITCAST9]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC12]](<2 x s16>)
; GFX9: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC13]](<2 x s16>)
; GFX9: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC14]](<2 x s16>)
@ -1053,17 +938,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC4]], [[TRUNC5]]
@ -1071,16 +953,13 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
@ -1088,16 +967,13 @@ body: |
; SI: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
; SI: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[ZEXT4]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY11]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY4]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
@ -1105,16 +981,13 @@ body: |
; SI: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC3]], [[C2]]
; SI: [[AND13:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C1]]
; SI: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[ZEXT6]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[ZEXT6]](s32)
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY15]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY5]](s32)
; SI: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR13]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]

715
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
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25
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
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@ -436,15 +436,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -492,15 +489,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@ -545,11 +539,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD2]](s16)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY2]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST4]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2

165
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
View File

@ -75,8 +75,7 @@ body: |
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C1]](s32), [[AND]]
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
@ -116,10 +115,8 @@ body: |
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX7: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@ -130,10 +127,8 @@ body: |
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@ -144,10 +139,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@ -172,43 +165,28 @@ body: |
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX7: $vgpr0 = COPY [[COPY5]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7: $vgpr0 = COPY [[SELECT]](s32)
; GFX8-LABEL: name: test_icmp_s24
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX8: $vgpr0 = COPY [[COPY5]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8: $vgpr0 = COPY [[SELECT]](s32)
; GFX9-LABEL: name: test_icmp_s24
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9: $vgpr0 = COPY [[COPY5]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX9: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s24) = G_CONSTANT i24 0
%1:_(s32) = COPY $vgpr0
%2:_(s24) = G_TRUNC %1
@ -232,10 +210,8 @@ body: |
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2s32
@ -247,10 +223,8 @@ body: |
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2s32
@ -292,12 +266,9 @@ body: |
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX8-LABEL: name: test_icmp_v3s32
@ -312,12 +283,9 @@ body: |
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX9-LABEL: name: test_icmp_v3s32
@ -365,14 +333,10 @@ body: |
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX7: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX8-LABEL: name: test_icmp_v4s32
@ -390,14 +354,10 @@ body: |
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX8: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX9-LABEL: name: test_icmp_v4s32
@ -657,10 +617,8 @@ body: |
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p3
@ -672,10 +630,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p3
@ -712,10 +668,8 @@ body: |
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p999
@ -727,10 +681,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p999
@ -769,15 +721,11 @@ body: |
; GFX7: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND2]](s32), [[AND3]]
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; GFX7: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
@ -846,32 +794,23 @@ body: |
; GFX7-LABEL: name: test_icmp_s33
; GFX7: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX7: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX7: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; GFX7: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; GFX7: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; GFX7: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1)
; GFX8-LABEL: name: test_icmp_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX8: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1)
; GFX9-LABEL: name: test_icmp_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
; GFX9: S_ENDPGM 0, implicit [[ICMP]](s1)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0

308
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
View File

@ -14,278 +14,216 @@ body: |
; TAHITI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; TAHITI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; TAHITI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY]](s32)
; TAHITI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; TAHITI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; TAHITI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY1]](s32)
; TAHITI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
; TAHITI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY2]](s32)
; TAHITI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; TAHITI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY3]](s32)
; TAHITI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
; TAHITI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY4]](s32)
; TAHITI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; TAHITI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; TAHITI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY10]](s32)
; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY5]](s32)
; TAHITI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; TAHITI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
; TAHITI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY12]](s32)
; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY6]](s32)
; TAHITI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; TAHITI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C2]]
; TAHITI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY14]](s32)
; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY7]](s32)
; TAHITI: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; TAHITI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
; TAHITI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY16]](s32)
; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY8]](s32)
; TAHITI: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; TAHITI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
; TAHITI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY18]](s32)
; TAHITI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY9]](s32)
; TAHITI: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; TAHITI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
; TAHITI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY20]](s32)
; TAHITI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY10]](s32)
; TAHITI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; TAHITI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
; TAHITI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY22]](s32)
; TAHITI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY11]](s32)
; TAHITI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; TAHITI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C2]]
; TAHITI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY24]](s32)
; TAHITI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY12]](s32)
; TAHITI: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; TAHITI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C2]]
; TAHITI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY26]](s32)
; TAHITI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY13]](s32)
; TAHITI: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; TAHITI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C2]]
; TAHITI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY28]](s32)
; TAHITI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; TAHITI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C2]]
; TAHITI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY30]](s32)
; TAHITI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; TAHITI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C2]]
; TAHITI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY32]](s32)
; TAHITI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C2]]
; TAHITI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY34]](s32)
; TAHITI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C2]]
; TAHITI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY36]](s32)
; TAHITI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C2]]
; TAHITI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY38]](s32)
; TAHITI: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C2]]
; TAHITI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY40]](s32)
; TAHITI: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C2]]
; TAHITI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY42]](s32)
; TAHITI: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C2]]
; TAHITI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY44]](s32)
; TAHITI: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[COPY47:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C2]]
; TAHITI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY46]](s32)
; TAHITI: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[COPY49:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C2]]
; TAHITI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY48]](s32)
; TAHITI: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C2]]
; TAHITI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY50]](s32)
; TAHITI: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[COPY53:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C2]]
; TAHITI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY52]](s32)
; TAHITI: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[COPY55:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C2]]
; TAHITI: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY54]](s32)
; TAHITI: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C2]]
; TAHITI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY56]](s32)
; TAHITI: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[COPY59:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C2]]
; TAHITI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY58]](s32)
; TAHITI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY14]](s32)
; TAHITI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; TAHITI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY15]](s32)
; TAHITI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; TAHITI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY16]](s32)
; TAHITI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY17]](s32)
; TAHITI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY18]](s32)
; TAHITI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY19]](s32)
; TAHITI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY20]](s32)
; TAHITI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY21]](s32)
; TAHITI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY22]](s32)
; TAHITI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY23]](s32)
; TAHITI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY24]](s32)
; TAHITI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY25]](s32)
; TAHITI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY26]](s32)
; TAHITI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY27]](s32)
; TAHITI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY28]](s32)
; TAHITI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; TAHITI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY29]](s32)
; TAHITI: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; TAHITI: [[COPY60:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C1]]
; TAHITI: [[COPY61:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; TAHITI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C1]]
; TAHITI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
; TAHITI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; TAHITI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C1]](s32)
; TAHITI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND30]], [[SHL]]
; TAHITI: [[COPY62:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; TAHITI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C1]]
; TAHITI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; TAHITI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C3]](s32)
; TAHITI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; TAHITI: [[COPY63:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; TAHITI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C1]]
; TAHITI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; TAHITI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND33]], [[C4]](s32)
; TAHITI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; TAHITI: [[COPY64:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; TAHITI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY64]], [[C1]]
; TAHITI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; TAHITI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C5]](s32)
; TAHITI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
; TAHITI: [[COPY65:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; TAHITI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY65]], [[C1]]
; TAHITI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; TAHITI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C6]](s32)
; TAHITI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; TAHITI: [[COPY66:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; TAHITI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY66]], [[C1]]
; TAHITI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; TAHITI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C7]](s32)
; TAHITI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; TAHITI: [[COPY67:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; TAHITI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY67]], [[C1]]
; TAHITI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; TAHITI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C8]](s32)
; TAHITI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; TAHITI: [[COPY68:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; TAHITI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY68]], [[C1]]
; TAHITI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C1]]
; TAHITI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C9]](s32)
; TAHITI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
; TAHITI: [[COPY69:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
; TAHITI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY69]], [[C1]]
; TAHITI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C1]]
; TAHITI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C10]](s32)
; TAHITI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; TAHITI: [[COPY70:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; TAHITI: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY70]], [[C1]]
; TAHITI: [[AND40:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C1]]
; TAHITI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C11]](s32)
; TAHITI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
; TAHITI: [[COPY71:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
; TAHITI: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY71]], [[C1]]
; TAHITI: [[AND41:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C1]]
; TAHITI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[C12]](s32)
; TAHITI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
; TAHITI: [[COPY72:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; TAHITI: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY72]], [[C1]]
; TAHITI: [[AND42:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C1]]
; TAHITI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C13]](s32)
; TAHITI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; TAHITI: [[COPY73:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
; TAHITI: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY73]], [[C1]]
; TAHITI: [[AND43:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C1]]
; TAHITI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C14]](s32)
; TAHITI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
; TAHITI: [[COPY74:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
; TAHITI: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY74]], [[C1]]
; TAHITI: [[AND44:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C1]]
; TAHITI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C15]](s32)
; TAHITI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; TAHITI: [[COPY75:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
; TAHITI: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY75]], [[C1]]
; TAHITI: [[AND45:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C1]]
; TAHITI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C16]](s32)
; TAHITI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; TAHITI: [[COPY76:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY76]], [[C1]]
; TAHITI: [[AND46:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; TAHITI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C]](s32)
; TAHITI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; TAHITI: [[COPY77:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
; TAHITI: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY77]], [[C1]]
; TAHITI: [[AND47:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C1]]
; TAHITI: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; TAHITI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C17]](s32)
; TAHITI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
; TAHITI: [[COPY78:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
; TAHITI: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY78]], [[C1]]
; TAHITI: [[AND48:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C1]]
; TAHITI: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
; TAHITI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C18]](s32)
; TAHITI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; TAHITI: [[COPY79:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
; TAHITI: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY79]], [[C1]]
; TAHITI: [[AND49:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C1]]
; TAHITI: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; TAHITI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND49]], [[C19]](s32)
; TAHITI: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
; TAHITI: [[COPY80:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
; TAHITI: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY80]], [[C1]]
; TAHITI: [[AND50:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C1]]
; TAHITI: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; TAHITI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C20]](s32)
; TAHITI: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
; TAHITI: [[COPY81:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
; TAHITI: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY81]], [[C1]]
; TAHITI: [[AND51:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C1]]
; TAHITI: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
; TAHITI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C21]](s32)
; TAHITI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; TAHITI: [[COPY82:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
; TAHITI: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY82]], [[C1]]
; TAHITI: [[AND52:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C1]]
; TAHITI: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
; TAHITI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C22]](s32)
; TAHITI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
; TAHITI: [[COPY83:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
; TAHITI: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY83]], [[C1]]
; TAHITI: [[AND53:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C1]]
; TAHITI: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; TAHITI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C23]](s32)
; TAHITI: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
; TAHITI: [[COPY84:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
; TAHITI: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY84]], [[C1]]
; TAHITI: [[AND54:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C1]]
; TAHITI: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; TAHITI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C24]](s32)
; TAHITI: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; TAHITI: [[COPY85:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
; TAHITI: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY85]], [[C1]]
; TAHITI: [[AND55:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C1]]
; TAHITI: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; TAHITI: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C25]](s32)
; TAHITI: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
; TAHITI: [[COPY86:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
; TAHITI: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY86]], [[C1]]
; TAHITI: [[AND56:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C1]]
; TAHITI: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; TAHITI: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C26]](s32)
; TAHITI: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
; TAHITI: [[COPY87:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
; TAHITI: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY87]], [[C1]]
; TAHITI: [[AND57:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C1]]
; TAHITI: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
; TAHITI: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND57]], [[C27]](s32)
; TAHITI: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
; TAHITI: [[COPY88:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
; TAHITI: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY88]], [[C1]]
; TAHITI: [[AND58:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C1]]
; TAHITI: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; TAHITI: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C28]](s32)
; TAHITI: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; TAHITI: [[COPY89:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
; TAHITI: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY89]], [[C1]]
; TAHITI: [[AND59:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C1]]
; TAHITI: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; TAHITI: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C29]](s32)
; TAHITI: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
; TAHITI: [[COPY90:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
; TAHITI: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY90]], [[C1]]
; TAHITI: [[AND60:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C1]]
; TAHITI: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
; TAHITI: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C30]](s32)
; TAHITI: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
; TAHITI: [[COPY91:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
; TAHITI: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY91]], [[C1]]
; TAHITI: [[AND61:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C1]]
; TAHITI: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; TAHITI: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C31]](s32)
; TAHITI: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
@ -344,8 +282,7 @@ body: |
; FIJI: [[LSHR30:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C15]](s16)
; FIJI: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; FIJI: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FIJI: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; FIJI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C16]]
; FIJI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C16]]
; FIJI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; FIJI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C16]]
; FIJI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C16]](s32)
@ -420,8 +357,7 @@ body: |
; FIJI: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; FIJI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C30]](s32)
; FIJI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; FIJI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; FIJI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C16]]
; FIJI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C16]]
; FIJI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C]](s32)
; FIJI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; FIJI: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR16]](s16)

23
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
View File

@ -22,8 +22,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_s7
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[DEF]](s32)
%0:_(s7) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
@ -36,8 +35,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_s8
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[DEF]](s32)
%0:_(s8) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
@ -75,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_48
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](s64)
%0:_(s48) = G_IMPLICIT_DEF
%1:_(s64) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
@ -366,8 +363,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_v2s1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
@ -380,8 +376,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_v3s1
; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY]](<3 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[DEF]](<3 x s32>)
%0:_(<3 x s1>) = G_IMPLICIT_DEF
%1:_(<3 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1_vgpr2 = COPY %1
@ -394,8 +389,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_v2s8
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
%0:_(<2 x s8>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
@ -411,10 +405,7 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s8>) = G_IMPLICIT_DEF
%1:_(<3 x s32>) = G_ANYEXT %0

49
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
View File

@ -146,11 +146,8 @@ body: |
; CHECK-LABEL: name: insert_vector_elt_0_v2i8_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY1]], [[COPY2]](s32), 0
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY [[INSERT]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY3]](<2 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[DEF]], [[COPY]](s32), 0
; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(<2 x s8>) = G_IMPLICIT_DEF
@ -803,25 +800,20 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[SHL3]](s32)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[SHL3]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@ -831,18 +823,14 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C]](s32)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C1]](s32)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C2]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]]
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL6]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL7]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL8]]
; CHECK: $vgpr0 = COPY [[OR6]](s32)
@ -880,15 +868,13 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
@ -896,14 +882,12 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@ -917,8 +901,7 @@ body: |
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[SHL6]](s32)
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[SHL6]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1

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