From 2baef8f466447d8621be9e8bfbb6b14e7baba2a4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 18 Dec 2016 04:17:00 +0000 Subject: [PATCH] [AVX-512] Make sure VLX is also enabled before using EVEX encoded logic ops for scalars. I missed this in r290049. llvm-svn: 290055 --- llvm/lib/Target/X86/X86InstrAVX512.td | 2 +- llvm/lib/Target/X86/X86InstrSSE.td | 2 +- llvm/test/CodeGen/X86/fp-logic-replace.ll | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index ac226e6c6ff3..03ba06d1f6dc 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -4559,7 +4559,7 @@ defm : avx512_fp_logical_lowering_sizes<"VPOR", or>; defm : avx512_fp_logical_lowering_sizes<"VPXOR", xor>; defm : avx512_fp_logical_lowering_sizes<"VPANDN", X86andnp>; -let Predicates = [HasDQI] in { +let Predicates = [HasVLX,HasDQI] in { // Use packed logical operations for scalar ops. def : Pat<(f64 (X86fand FR64X:$src1, FR64X:$src2)), (COPY_TO_REGCLASS (VANDPDZ128rr diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 6f344fcd7d64..734c8a8f747c 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -2932,7 +2932,7 @@ let Predicates = [HasAVX, NoVLX_Or_NoDQI] in { (VANDNPDYrm VR256:$src1, addr:$src2)>; } -let Predicates = [HasAVX, NoDQI] in { +let Predicates = [HasAVX, NoVLX_Or_NoDQI] in { // Use packed logical operations for scalar ops. def : Pat<(f64 (X86fand FR64:$src1, FR64:$src2)), (COPY_TO_REGCLASS (VANDPDrr diff --git a/llvm/test/CodeGen/X86/fp-logic-replace.ll b/llvm/test/CodeGen/X86/fp-logic-replace.ll index 628e99f88592..ac3da445ed6a 100644 --- a/llvm/test/CodeGen/X86/fp-logic-replace.ll +++ b/llvm/test/CodeGen/X86/fp-logic-replace.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq | FileCheck %s --check-prefix=AVX512DQ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=AVX512DQ ; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction. ; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels