forked from OSchip/llvm-project
[libunwind] [sparc] Add SPARCv9 support
Adds libunwind support for SPARCv9 (aka sparc64). This is a rebase of @kettenis' patch D32450, which I created (with his permission) because the original review has become inactive. The changes are of a cosmetic nature to make it fit better with the new code style, and to reuse the existing SPARCv8 code, whenever possible. Please let me know if I posted this on the wrong place. Also, the summary of the original review is reproduced below: > This adds unwinder support for 64-bit SPARC (aka SPARCv9). The implementation was done on OpenBSD/sparc64, so it takes StackGhost into account: > > https://www.usenix.org/legacy/publications/library/proceedings/sec01/full_papers/frantzen/frantzen_html/index.html > > Since StackGhost xor's return addresses with a random cookie before storing them on the stack, the unwinder has to do some extra work to recover those. This is done by introducing a new kRegisterInCFADecrypt "location" type that is used to implement the DW_CFA_GNU_window_save opcode. That implementation is SPARC-specific, but should work for 32-bit SPARC as well. DW_CFA_GNU_window_save is only ever generated on SPARC as far as I know. Co-authored-by: Mark Kettenis Reviewed By: #libunwind, thesamesam, MaskRay, Arfrever Differential Revision: https://reviews.llvm.org/D116857
This commit is contained in:
Koakuma
Fangrui Song
parent
527654dceb
commit
2b9554b885
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@ -23,6 +23,7 @@
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64 31
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON 34
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE 143
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@ -125,6 +126,12 @@
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# error "Unsupported MIPS ABI and/or environment"
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# endif
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
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#elif defined(__sparc__) && defined(__arch64__)
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#define _LIBUNWIND_TARGET_SPARC64 1
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER \
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_LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64
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#define _LIBUNWIND_CONTEXT_SIZE 33
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#define _LIBUNWIND_CURSOR_SIZE 45
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# elif defined(__sparc__)
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#define _LIBUNWIND_TARGET_SPARC 1
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
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@ -165,6 +172,7 @@
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# define _LIBUNWIND_TARGET_MIPS_O32 1
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# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
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# define _LIBUNWIND_TARGET_SPARC 1
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# define _LIBUNWIND_TARGET_SPARC64 1
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# define _LIBUNWIND_TARGET_HEXAGON 1
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# define _LIBUNWIND_TARGET_RISCV 1
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# define _LIBUNWIND_TARGET_VE 1
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@ -74,6 +74,13 @@ private:
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}
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};
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template <typename R>
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auto getSparcWCookie(const R &r, int) -> decltype(r.getWCookie()) {
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return r.getWCookie();
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}
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template <typename R> uint64_t getSparcWCookie(const R &, long) {
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return 0;
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}
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template <typename A, typename R>
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typename A::pint_t DwarfInstructions<A, R>::getSavedRegister(
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@ -83,6 +90,10 @@ typename A::pint_t DwarfInstructions<A, R>::getSavedRegister(
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case CFI_Parser<A>::kRegisterInCFA:
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return (pint_t)addressSpace.getRegister(cfa + (pint_t)savedReg.value);
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case CFI_Parser<A>::kRegisterInCFADecrypt: // sparc64 specific
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return addressSpace.getP(cfa + (pint_t)savedReg.value) ^
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getSparcWCookie(registers, 0);
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case CFI_Parser<A>::kRegisterAtExpression:
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return (pint_t)addressSpace.getRegister(evaluateExpression(
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(pint_t)savedReg.value, addressSpace, registers, cfa));
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@ -124,6 +135,7 @@ double DwarfInstructions<A, R>::getSavedFloatRegister(
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case CFI_Parser<A>::kRegisterIsExpression:
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case CFI_Parser<A>::kRegisterUnused:
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case CFI_Parser<A>::kRegisterOffsetFromCFA:
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case CFI_Parser<A>::kRegisterInCFADecrypt:
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// FIX ME
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break;
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}
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@ -148,6 +160,7 @@ v128 DwarfInstructions<A, R>::getSavedVectorRegister(
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case CFI_Parser<A>::kRegisterUndefined:
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case CFI_Parser<A>::kRegisterOffsetFromCFA:
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case CFI_Parser<A>::kRegisterInRegister:
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case CFI_Parser<A>::kRegisterInCFADecrypt:
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// FIX ME
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break;
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}
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@ -266,6 +279,12 @@ int DwarfInstructions<A, R>::stepWithDwarf(A &addressSpace, pint_t pc,
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}
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC64)
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// Skip call site instruction and delay slot.
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if (R::getArch() == REGISTERS_SPARC64)
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returnAddress += 8;
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#endif
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#if defined(_LIBUNWIND_TARGET_PPC64)
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#define PPC64_ELFV1_R2_LOAD_INST_ENCODING 0xe8410028u // ld r2,40(r1)
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#define PPC64_ELFV1_R2_OFFSET 40
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@ -71,6 +71,7 @@ public:
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kRegisterUnused,
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kRegisterUndefined,
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kRegisterInCFA,
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kRegisterInCFADecrypt, // sparc64 specific
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kRegisterOffsetFromCFA,
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kRegisterInRegister,
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kRegisterAtExpression,
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@ -733,7 +734,8 @@ bool CFI_Parser<A>::parseFDEInstructions(A &addressSpace,
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"DW_CFA_GNU_negative_offset_extended(%" PRId64 ")\n", offset);
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break;
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#if defined(_LIBUNWIND_TARGET_AARCH64) || defined(_LIBUNWIND_TARGET_SPARC)
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#if defined(_LIBUNWIND_TARGET_AARCH64) || defined(_LIBUNWIND_TARGET_SPARC) || \
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defined(_LIBUNWIND_TARGET_SPARC64)
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// The same constant is used to represent different instructions on
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// AArch64 (negate_ra_state) and SPARC (window_save).
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static_assert(DW_CFA_AARCH64_negate_ra_state == DW_CFA_GNU_window_save,
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@ -767,8 +769,31 @@ bool CFI_Parser<A>::parseFDEInstructions(A &addressSpace,
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}
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break;
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC64)
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// case DW_CFA_GNU_window_save:
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case REGISTERS_SPARC64:
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// Don't save %o0-%o7 on sparc64.
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// https://reviews.llvm.org/D32450#736405
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for (reg = UNW_SPARC_L0; reg <= UNW_SPARC_I7; reg++) {
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if (reg == UNW_SPARC_I7)
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results->setRegister(
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reg, kRegisterInCFADecrypt,
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static_cast<int64_t>((reg - UNW_SPARC_L0) * sizeof(pint_t)),
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initialState);
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else
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results->setRegister(
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reg, kRegisterInCFA,
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static_cast<int64_t>((reg - UNW_SPARC_L0) * sizeof(pint_t)),
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initialState);
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}
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_LIBUNWIND_TRACE_DWARF("DW_CFA_GNU_window_save\n");
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break;
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#endif
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}
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break;
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#else
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(void)arch;
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#endif
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@ -35,6 +35,7 @@ enum {
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REGISTERS_MIPS_O32,
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REGISTERS_MIPS_NEWABI,
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REGISTERS_SPARC,
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REGISTERS_SPARC64,
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REGISTERS_HEXAGON,
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REGISTERS_RISCV,
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REGISTERS_VE,
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@ -3586,6 +3587,191 @@ inline const char *Registers_sparc::getRegisterName(int regNum) {
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}
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#endif // _LIBUNWIND_TARGET_SPARC
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#if defined(_LIBUNWIND_TARGET_SPARC64)
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/// Registers_sparc64 holds the register state of a thread in a 64-bit
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/// sparc process.
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class _LIBUNWIND_HIDDEN Registers_sparc64 {
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public:
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Registers_sparc64() = default;
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Registers_sparc64(const void *registers);
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bool validRegister(int num) const;
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uint64_t getRegister(int num) const;
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void setRegister(int num, uint64_t value);
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bool validFloatRegister(int num) const;
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double getFloatRegister(int num) const;
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void setFloatRegister(int num, double value);
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bool validVectorRegister(int num) const;
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v128 getVectorRegister(int num) const;
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void setVectorRegister(int num, v128 value);
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const char *getRegisterName(int num);
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void jumpto();
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static int lastDwarfRegNum() {
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return _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64;
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}
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static int getArch() { return REGISTERS_SPARC64; }
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uint64_t getSP() const { return _registers.__regs[UNW_SPARC_O6] + 2047; }
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void setSP(uint64_t value) { _registers.__regs[UNW_SPARC_O6] = value - 2047; }
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uint64_t getIP() const { return _registers.__regs[UNW_SPARC_O7]; }
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void setIP(uint64_t value) { _registers.__regs[UNW_SPARC_O7] = value; }
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uint64_t getWCookie() const { return _wcookie; }
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private:
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struct sparc64_thread_state_t {
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uint64_t __regs[32];
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};
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sparc64_thread_state_t _registers{};
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uint64_t _wcookie = 0;
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};
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inline Registers_sparc64::Registers_sparc64(const void *registers) {
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static_assert((check_fit<Registers_sparc64, unw_context_t>::does_fit),
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"sparc64 registers do not fit into unw_context_t");
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memcpy(&_registers, registers, sizeof(_registers));
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memcpy(&_wcookie,
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static_cast<const uint8_t *>(registers) + sizeof(_registers),
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sizeof(_wcookie));
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}
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inline bool Registers_sparc64::validRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return true;
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if (regNum == UNW_REG_SP)
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return true;
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if (regNum < 0)
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return false;
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if (regNum <= UNW_SPARC_I7)
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return true;
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return false;
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}
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inline uint64_t Registers_sparc64::getRegister(int regNum) const {
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if (regNum >= UNW_SPARC_G0 && regNum <= UNW_SPARC_I7)
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return _registers.__regs[regNum];
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switch (regNum) {
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case UNW_REG_IP:
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return _registers.__regs[UNW_SPARC_O7];
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case UNW_REG_SP:
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return _registers.__regs[UNW_SPARC_O6] + 2047;
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}
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_LIBUNWIND_ABORT("unsupported sparc64 register");
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}
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inline void Registers_sparc64::setRegister(int regNum, uint64_t value) {
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if (regNum >= UNW_SPARC_G0 && regNum <= UNW_SPARC_I7) {
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_registers.__regs[regNum] = value;
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return;
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}
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switch (regNum) {
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case UNW_REG_IP:
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_registers.__regs[UNW_SPARC_O7] = value;
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return;
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case UNW_REG_SP:
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_registers.__regs[UNW_SPARC_O6] = value - 2047;
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return;
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}
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_LIBUNWIND_ABORT("unsupported sparc64 register");
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}
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inline bool Registers_sparc64::validFloatRegister(int) const { return false; }
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inline double Registers_sparc64::getFloatRegister(int) const {
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_LIBUNWIND_ABORT("no sparc64 float registers");
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}
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inline void Registers_sparc64::setFloatRegister(int, double) {
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_LIBUNWIND_ABORT("no sparc64 float registers");
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}
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inline bool Registers_sparc64::validVectorRegister(int) const { return false; }
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inline v128 Registers_sparc64::getVectorRegister(int) const {
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_LIBUNWIND_ABORT("no sparc64 vector registers");
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}
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inline void Registers_sparc64::setVectorRegister(int, v128) {
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_LIBUNWIND_ABORT("no sparc64 vector registers");
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}
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inline const char *Registers_sparc64::getRegisterName(int regNum) {
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switch (regNum) {
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case UNW_REG_IP:
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return "pc";
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case UNW_SPARC_G0:
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return "g0";
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case UNW_SPARC_G1:
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return "g1";
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case UNW_SPARC_G2:
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return "g2";
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case UNW_SPARC_G3:
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return "g3";
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case UNW_SPARC_G4:
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return "g4";
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case UNW_SPARC_G5:
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return "g5";
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case UNW_SPARC_G6:
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return "g6";
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case UNW_SPARC_G7:
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return "g7";
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case UNW_SPARC_O0:
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return "o0";
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case UNW_SPARC_O1:
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return "o1";
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case UNW_SPARC_O2:
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return "o2";
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case UNW_SPARC_O3:
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return "o3";
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case UNW_SPARC_O4:
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return "o4";
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case UNW_SPARC_O5:
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return "o5";
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case UNW_REG_SP:
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case UNW_SPARC_O6:
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return "o6";
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case UNW_SPARC_O7:
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return "o7";
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case UNW_SPARC_L0:
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return "l0";
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case UNW_SPARC_L1:
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return "l1";
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case UNW_SPARC_L2:
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return "l2";
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case UNW_SPARC_L3:
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return "l3";
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case UNW_SPARC_L4:
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return "l4";
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case UNW_SPARC_L5:
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return "l5";
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case UNW_SPARC_L6:
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return "l6";
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case UNW_SPARC_L7:
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return "l7";
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case UNW_SPARC_I0:
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return "i0";
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case UNW_SPARC_I1:
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return "i1";
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case UNW_SPARC_I2:
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return "i2";
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case UNW_SPARC_I3:
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return "i3";
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case UNW_SPARC_I4:
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return "i4";
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case UNW_SPARC_I5:
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return "i5";
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case UNW_SPARC_I6:
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return "i6";
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case UNW_SPARC_I7:
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return "i7";
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default:
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return "unknown register";
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}
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}
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#endif // _LIBUNWIND_TARGET_SPARC64
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#if defined(_LIBUNWIND_TARGET_HEXAGON)
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/// Registers_hexagon holds the register state of a thread in a Hexagon QDSP6
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/// process.
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@ -1032,6 +1032,10 @@ private:
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int stepWithCompactEncoding(Registers_sparc &) { return UNW_EINVAL; }
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC64)
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int stepWithCompactEncoding(Registers_sparc64 &) { return UNW_EINVAL; }
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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int stepWithCompactEncoding(Registers_riscv &) {
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return UNW_EINVAL;
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@ -1104,6 +1108,12 @@ private:
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bool compactSaysUseDwarf(Registers_sparc &, uint32_t *) const { return true; }
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC64)
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bool compactSaysUseDwarf(Registers_sparc64 &, uint32_t *) const {
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return true;
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}
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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bool compactSaysUseDwarf(Registers_riscv &, uint32_t *) const {
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return true;
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@ -1182,6 +1192,12 @@ private:
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compact_unwind_encoding_t dwarfEncoding(Registers_sparc &) const { return 0; }
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC64)
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compact_unwind_encoding_t dwarfEncoding(Registers_sparc64 &) const {
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return 0;
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}
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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compact_unwind_encoding_t dwarfEncoding(Registers_riscv &) const {
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return 0;
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@ -1062,6 +1062,53 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
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ld $4, (8 * 4)($4)
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.set pop
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#elif defined(__sparc__) && defined(__arch64__)
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DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind17Registers_sparc646jumptoEv)
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//
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// void libunwind::Registers_sparc64::jumpto()
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//
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// On entry:
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// thread_state pointer is in %o0
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//
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.register %g2, #scratch
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.register %g3, #scratch
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.register %g6, #scratch
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.register %g7, #scratch
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flushw
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ldx [%o0 + 0x08], %g1
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ldx [%o0 + 0x10], %g2
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ldx [%o0 + 0x18], %g3
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ldx [%o0 + 0x20], %g4
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ldx [%o0 + 0x28], %g5
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ldx [%o0 + 0x30], %g6
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ldx [%o0 + 0x38], %g7
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ldx [%o0 + 0x48], %o1
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ldx [%o0 + 0x50], %o2
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ldx [%o0 + 0x58], %o3
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ldx [%o0 + 0x60], %o4
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ldx [%o0 + 0x68], %o5
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ldx [%o0 + 0x70], %o6
|
||||
ldx [%o0 + 0x78], %o7
|
||||
ldx [%o0 + 0x80], %l0
|
||||
ldx [%o0 + 0x88], %l1
|
||||
ldx [%o0 + 0x90], %l2
|
||||
ldx [%o0 + 0x98], %l3
|
||||
ldx [%o0 + 0xa0], %l4
|
||||
ldx [%o0 + 0xa8], %l5
|
||||
ldx [%o0 + 0xb0], %l6
|
||||
ldx [%o0 + 0xb8], %l7
|
||||
ldx [%o0 + 0xc0], %i0
|
||||
ldx [%o0 + 0xc8], %i1
|
||||
ldx [%o0 + 0xd0], %i2
|
||||
ldx [%o0 + 0xd8], %i3
|
||||
ldx [%o0 + 0xe0], %i4
|
||||
ldx [%o0 + 0xe8], %i5
|
||||
ldx [%o0 + 0xf0], %i6
|
||||
ldx [%o0 + 0xf8], %i7
|
||||
jmp %o7
|
||||
ldx [%o0 + 0x40], %o0
|
||||
|
||||
#elif defined(__sparc__)
|
||||
|
||||
//
|
||||
|
|
|
|||
|
|
@ -999,6 +999,64 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
|||
|
||||
jumpr r31
|
||||
|
||||
#elif defined(__sparc__) && defined(__arch64__)
|
||||
|
||||
#
|
||||
# extern int __unw_getcontext(unw_context_t* thread_state)
|
||||
#
|
||||
# On entry:
|
||||
# thread_state pointer is in %o0
|
||||
#
|
||||
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
||||
.register %g2, #scratch
|
||||
.register %g3, #scratch
|
||||
.register %g6, #scratch
|
||||
.register %g7, #scratch
|
||||
stx %g1, [%o0 + 0x08]
|
||||
stx %g2, [%o0 + 0x10]
|
||||
stx %g3, [%o0 + 0x18]
|
||||
stx %g4, [%o0 + 0x20]
|
||||
stx %g5, [%o0 + 0x28]
|
||||
stx %g6, [%o0 + 0x30]
|
||||
stx %g7, [%o0 + 0x38]
|
||||
stx %o0, [%o0 + 0x40]
|
||||
stx %o1, [%o0 + 0x48]
|
||||
stx %o2, [%o0 + 0x50]
|
||||
stx %o3, [%o0 + 0x58]
|
||||
stx %o4, [%o0 + 0x60]
|
||||
stx %o5, [%o0 + 0x68]
|
||||
stx %o6, [%o0 + 0x70]
|
||||
stx %o7, [%o0 + 0x78]
|
||||
stx %l0, [%o0 + 0x80]
|
||||
stx %l1, [%o0 + 0x88]
|
||||
stx %l2, [%o0 + 0x90]
|
||||
stx %l3, [%o0 + 0x98]
|
||||
stx %l4, [%o0 + 0xa0]
|
||||
stx %l5, [%o0 + 0xa8]
|
||||
stx %l6, [%o0 + 0xb0]
|
||||
stx %l7, [%o0 + 0xb8]
|
||||
stx %i0, [%o0 + 0xc0]
|
||||
stx %i1, [%o0 + 0xc8]
|
||||
stx %i2, [%o0 + 0xd0]
|
||||
stx %i3, [%o0 + 0xd8]
|
||||
stx %i4, [%o0 + 0xe0]
|
||||
stx %i5, [%o0 + 0xe8]
|
||||
stx %i6, [%o0 + 0xf0]
|
||||
stx %i7, [%o0 + 0xf8]
|
||||
|
||||
# save StackGhost cookie
|
||||
mov %i7, %g4
|
||||
save %sp, -176, %sp
|
||||
# register window flush necessary even without StackGhost
|
||||
flushw
|
||||
restore
|
||||
ldx [%sp + 2047 + 0x78], %g5
|
||||
xor %g4, %g5, %g4
|
||||
stx %g4, [%o0 + 0x100]
|
||||
retl
|
||||
# return UNW_ESUCCESS
|
||||
clr %o0
|
||||
|
||||
#elif defined(__sparc__)
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -67,6 +67,8 @@ _LIBUNWIND_HIDDEN int __unw_init_local(unw_cursor_t *cursor,
|
|||
# define REGISTER_KIND Registers_mips_newabi
|
||||
#elif defined(__mips__)
|
||||
# warning The MIPS architecture is not supported with this ABI and environment!
|
||||
#elif defined(__sparc__) && defined(__arch64__)
|
||||
#define REGISTER_KIND Registers_sparc64
|
||||
#elif defined(__sparc__)
|
||||
# define REGISTER_KIND Registers_sparc
|
||||
#elif defined(__riscv)
|
||||
|
|
|
|||
Loading…
Reference in New Issue