forked from OSchip/llvm-project
Make EXTRACT_VECTOR_ELT a bit more flexible in terms of the returned
value. Adjust other code to deal with that correctly. Make DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT take advantage of this new flexibility to simplify the code and make it deal with unusual vectors (like <4 x i1>) correctly. Fixes PR3037. llvm-svn: 75176
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@ -303,7 +303,9 @@ namespace ISD {
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INSERT_VECTOR_ELT,
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/// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
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/// identified by the (potentially variable) element number IDX.
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/// identified by the (potentially variable) element number IDX. If the
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/// return type is an integer type larger than the element type of the
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/// vector, the result is extended to the width of the return type.
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EXTRACT_VECTOR_ELT,
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/// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
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@ -1526,7 +1526,11 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
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StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
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if (Op.getValueType().isVector())
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return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
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else
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return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
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NULL, 0, Vec.getValueType().getVectorElementType());
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}
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SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
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@ -303,52 +303,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
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MVT OldVT = N->getValueType(0);
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SDValue OldVec = N->getOperand(0);
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if (getTypeAction(OldVec.getValueType()) == WidenVector)
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OldVec = GetWidenedVector(N->getOperand(0));
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unsigned OldElts = OldVec.getValueType().getVectorNumElements();
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DebugLoc dl = N->getDebugLoc();
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if (OldElts == 1) {
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assert(!isTypeLegal(OldVec.getValueType()) &&
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"Legal one-element vector of a type needing promotion!");
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// It is tempting to follow GetScalarizedVector by a call to
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// GetPromotedInteger, but this would be wrong because the
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// scalarized value may not yet have been processed.
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return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
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GetScalarizedVector(OldVec));
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}
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// Convert to a vector half as long with an element type of twice the width,
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// for example <4 x i16> -> <2 x i32>.
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assert(!(OldElts & 1) && "Odd length vectors not supported!");
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MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
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assert(OldVT.isSimple() && NewVT.isSimple());
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SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
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MVT::getVectorVT(NewVT, OldElts / 2),
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OldVec);
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// Extract the element at OldIdx / 2 from the new vector.
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SDValue OldIdx = N->getOperand(1);
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SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
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DAG.getConstant(1, TLI.getPointerTy()));
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SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
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// Select the appropriate half of the element: Lo if OldIdx was even,
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// Hi if it was odd.
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SDValue Lo = Elt;
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SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
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DAG.getConstant(OldVT.getSizeInBits(),
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TLI.getPointerTy()));
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if (TLI.isBigEndian())
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std::swap(Lo, Hi);
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// Extend to the promoted type.
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SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
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SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
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return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
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MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
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N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
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@ -331,7 +331,11 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
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/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
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/// index.
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SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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return GetScalarizedVector(N->getOperand(0));
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SDValue Res = GetScalarizedVector(N->getOperand(0));
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if (Res.getValueType() != N->getValueType(0))
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Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
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Res);
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return Res;
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}
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/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
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@ -1052,7 +1056,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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// Load back the required element.
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StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
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return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0);
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return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
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SV, 0, EltVT);
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}
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SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
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@ -1904,9 +1909,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
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SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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SDValue InOp = GetWidenedVector(N->getOperand(0));
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MVT EltVT = InOp.getValueType().getVectorElementType();
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
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EltVT, InOp, N->getOperand(1));
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N->getValueType(0), InOp, N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
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@ -2693,13 +2693,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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// expanding large vector constants.
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if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
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SDValue Elt = N1.getOperand(N2C->getZExtValue());
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if (Elt.getValueType() != VT) {
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MVT VEltTy = N1.getValueType().getVectorElementType();
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if (Elt.getValueType() != VEltTy) {
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// If the vector element type is not legal, the BUILD_VECTOR operands
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// are promoted and implicitly truncated. Make that explicit here.
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assert(VT.isInteger() && Elt.getValueType().isInteger() &&
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VT.bitsLE(Elt.getValueType()) &&
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"Bad type for BUILD_VECTOR operand");
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Elt = getNode(ISD::TRUNCATE, DL, VT, Elt);
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Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt);
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}
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if (VT != VEltTy) {
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// If the vector element type is not legal, the EXTRACT_VECTOR_ELT
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// result is implicitly extended.
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Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt);
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}
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return Elt;
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}
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@ -0,0 +1,8 @@
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; RUN: llvm-as < %s | llc -march=x86 -disable-mmx
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define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind {
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%D = icmp sgt <2 x i32> %A, %B
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%E = zext <2 x i1> %D to <2 x i32>
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store <2 x i32> %E, <2 x i32>* %C
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ret void
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}
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@ -0,0 +1,11 @@
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; RUN: llvm-as < %s | llc -march=x86
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; PR3037
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define void @entry(<4 x i8>* %dest) {
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%1 = xor <4 x i1> zeroinitializer, < i1 true, i1 true, i1 true, i1 true >
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%2 = extractelement <4 x i1> %1, i32 3
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%3 = zext i1 %2 to i8
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%4 = insertelement <4 x i8> zeroinitializer, i8 %3, i32 3
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store <4 x i8> %4, <4 x i8>* %dest, align 1
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ret void
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}
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