forked from OSchip/llvm-project
[MIPS GlobalISel] Select count leading zeros
llvm.ctlz.<type> intrinsic has additional i1 argument is_zero_undef, it tells whether zero as the first argument produces a defined result. MIPS clz instruction returns 32 for zero input. G_CTLZ is generated from llvm.ctlz.<type> (<type> <src>, i1 false) intrinsics, clang generates these intrinsics from __builtin_clz and __builtin_clzll. G_CTLZ_ZERO_UNDEF can also be generated from llvm.ctlz with true as second argument. It is also traditionally part of and many algorithms that are now predicated on avoiding zero-value inputs. Add narrow scalar for G_CTLZ (algorithm uses G_CTLZ_ZERO_UNDEF). Lower G_CTLZ_ZERO_UNDEF and select G_CTLZ for MIPS32. Differential Revision: https://reviews.llvm.org/D73214
This commit is contained in:
Petar Avramovic
parent
941f20c3bd
commit
2b66d32f3f
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@ -241,6 +241,7 @@ public:
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LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerBitcast(MachineInstr &MI);
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LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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@ -977,8 +977,13 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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case TargetOpcode::G_CTTZ:
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case TargetOpcode::G_CTTZ_ZERO_UNDEF:
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case TargetOpcode::G_CTPOP:
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if (TypeIdx != 0)
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return UnableToLegalize; // TODO
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if (TypeIdx == 1)
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switch (MI.getOpcode()) {
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case TargetOpcode::G_CTLZ:
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return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);
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default:
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return UnableToLegalize;
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}
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Observer.changingInstr(MI);
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narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
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@ -3849,6 +3854,37 @@ LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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if (TypeIdx != 1)
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return UnableToLegalize;
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LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
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MachineIRBuilder &B = MIRBuilder;
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auto UnmergeSrc = B.buildUnmerge(NarrowTy, MI.getOperand(1));
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// ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)
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auto C_0 = B.buildConstant(NarrowTy, 0);
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auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
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UnmergeSrc.getReg(1), C_0);
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auto LoCTLZ = B.buildCTLZ(NarrowTy, UnmergeSrc.getReg(0));
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auto C_NarrowSize = B.buildConstant(NarrowTy, NarrowSize);
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auto HiIsZeroCTLZ = B.buildAdd(NarrowTy, LoCTLZ, C_NarrowSize);
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auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(NarrowTy, UnmergeSrc.getReg(1));
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auto LoOut = B.buildSelect(NarrowTy, HiIsZero, HiIsZeroCTLZ, HiCTLZ);
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B.buildMerge(MI.getOperand(0), {LoOut.getReg(0), C_0.getReg(0)});
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MI.eraseFromParent();
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return Legalized;
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}
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return UnableToLegalize;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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unsigned Opc = MI.getOpcode();
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@ -202,6 +202,12 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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.lowerFor({s32})
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_CTLZ)
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.legalFor({{s32, s32}})
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.maxScalar(1, s32);
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getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
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.lowerFor({{s32, s32}});
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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@ -453,6 +453,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_BRINDIRECT:
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case G_VASTART:
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case G_BSWAP:
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case G_CTLZ:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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break;
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case G_ADD:
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@ -0,0 +1,24 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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---
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name: ctlz_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: ctlz_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[CLZ:%[0-9]+]]:gpr32 = CLZ [[COPY]]
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; MIPS32: $v0 = COPY [[CLZ]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CTLZ %0(s32)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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@ -0,0 +1,57 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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---
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name: ctlz_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: ctlz_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
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; MIPS32: $v0 = COPY [[CTLZ]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_CTLZ %0(s32)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: ctlz_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: ctlz_i64
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
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; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
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; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[CTLZ1]]
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; MIPS32: $v0 = COPY [[SELECT]](s32)
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; MIPS32: $v1 = COPY [[C]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%1:_(s32) = COPY $a0
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%2:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
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%3:_(s64) = G_CTLZ %0(s64)
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%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
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$v0 = COPY %4(s32)
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$v1 = COPY %5(s32)
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RetRA implicit $v0, implicit $v1
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...
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@ -0,0 +1,34 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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define i32 @ctlz_i32(i32 %a) {
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; MIPS32-LABEL: ctlz_i32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: clz $2, $4
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%0 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
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ret i32 %0
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}
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declare i32 @llvm.ctlz.i32(i32, i1 immarg)
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define i64 @ctlz_i64(i64 %a) {
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; MIPS32-LABEL: ctlz_i64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: ori $3, $zero, 0
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; MIPS32-NEXT: sltiu $1, $5, 1
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; MIPS32-NEXT: clz $2, $4
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; MIPS32-NEXT: addiu $2, $2, 32
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; MIPS32-NEXT: clz $4, $5
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; MIPS32-NEXT: andi $1, $1, 1
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; MIPS32-NEXT: movn $4, $2, $1
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; MIPS32-NEXT: move $2, $4
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%0 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
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ret i64 %0
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}
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declare i64 @llvm.ctlz.i64(i64, i1 immarg)
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@ -0,0 +1,23 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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---
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name: ctlz_i32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: ctlz_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[CTLZ:%[0-9]+]]:gprb(s32) = G_CTLZ [[COPY]](s32)
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; MIPS32: $v0 = COPY [[CTLZ]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_CTLZ %0(s32)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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