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[X86] Merge extract_subvector(*_EXTEND) and extract_subvector(*_EXTEND_VECTOR_INREG) handling. NFCI. 

llvm-svn: 363808
This commit is contained in:
Simon Pilgrim 2019-06-19 14:25:27 +00:00
parent 8a2bd361eb
commit 2b309027ed
1 changed files with 8 additions and 12 deletions
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18
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -43538,26 +43538,22 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(X86ISD::VFPEXT, SDLoc(N), VT, InVec.getOperand(0));
}
}
if ((InOpcode == ISD::ANY_EXTEND || InOpcode == ISD::ZERO_EXTEND ||
InOpcode == ISD::SIGN_EXTEND) &&
if ((InOpcode == ISD::ANY_EXTEND ||
InOpcode == ISD::ANY_EXTEND_VECTOR_INREG ||
InOpcode == ISD::ZERO_EXTEND ||
InOpcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
InOpcode == ISD::SIGN_EXTEND ||
InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) &&
VT.is128BitVector() &&
InVec.getOperand(0).getSimpleValueType().is128BitVector()) {
unsigned ExtOp;
unsigned ExtOp = InOpcode;
switch (InOpcode) {
default: llvm_unreachable("Unknown extension opcode");
case ISD::ANY_EXTEND: ExtOp = ISD::ANY_EXTEND_VECTOR_INREG; break;
case ISD::SIGN_EXTEND: ExtOp = ISD::SIGN_EXTEND_VECTOR_INREG; break;
case ISD::ZERO_EXTEND: ExtOp = ISD::ZERO_EXTEND_VECTOR_INREG; break;
}
return DAG.getNode(ExtOp, SDLoc(N), VT, InVec.getOperand(0));
}
if ((InOpcode == ISD::ANY_EXTEND_VECTOR_INREG ||
InOpcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) &&
VT.is128BitVector() &&
InVec.getOperand(0).getSimpleValueType().is128BitVector()) {
return DAG.getNode(InOpcode, SDLoc(N), VT, InVec.getOperand(0));
}
}
return SDValue();