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[RISCV][NFC] Add helper function isVectorConfigInstr to reduce Repeated code. 

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D119924
This commit is contained in:
Chenbing.Zheng 2022-02-24 03:49:58 +00:00 committed by Ben Shi
parent 9f9ac3464e
commit 2ae92e19eb
1 changed files with 10 additions and 12 deletions
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22
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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@ -447,6 +447,12 @@ char RISCVInsertVSETVLI::ID = 0;
INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
false, false) false, false)
static bool isVectorConfigInstr(const MachineInstr &MI) {
return MI.getOpcode() == RISCV::PseudoVSETVLI ||
MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
MI.getOpcode() == RISCV::PseudoVSETIVLI;
}
static MachineInstr *elideCopies(MachineInstr *MI, static MachineInstr *elideCopies(MachineInstr *MI,
const MachineRegisterInfo *MRI) { const MachineRegisterInfo *MRI) {
while (true) { while (true) {
@ -655,9 +661,7 @@ bool RISCVInsertVSETVLI::needVSETVLI(const VSETVLIInfo &Require,
Require.getAVLReg().isVirtual() && !CurInfo.hasSEWLMULRatioOnly() && Require.getAVLReg().isVirtual() && !CurInfo.hasSEWLMULRatioOnly() &&
CurInfo.hasCompatibleVTYPE(Require, /*Strict*/ false)) { CurInfo.hasCompatibleVTYPE(Require, /*Strict*/ false)) {
if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) { if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
if (DefMI->getOpcode() == RISCV::PseudoVSETVLI || if (isVectorConfigInstr(*DefMI)) {
DefMI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
DefMI->getOpcode() == RISCV::PseudoVSETIVLI) {
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI); VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo)) if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo))
return false; return false;
@ -870,9 +874,7 @@ bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
BlockData &BBInfo = BlockInfo[MBB.getNumber()]; BlockData &BBInfo = BlockInfo[MBB.getNumber()];
for (const MachineInstr &MI : MBB) { for (const MachineInstr &MI : MBB) {
// If this is an explicit VSETVLI or VSETIVLI, update our state. // If this is an explicit VSETVLI or VSETIVLI, update our state.
if (MI.getOpcode() == RISCV::PseudoVSETVLI || if (isVectorConfigInstr(MI)) {
MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
MI.getOpcode() == RISCV::PseudoVSETIVLI) {
HadVectorOp = true; HadVectorOp = true;
BBInfo.Change = getInfoForVSETVLI(MI); BBInfo.Change = getInfoForVSETVLI(MI);
continue; continue;
@ -983,9 +985,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
// We need the PHI input to the be the output of a VSET(I)VLI. // We need the PHI input to the be the output of a VSET(I)VLI.
MachineInstr *DefMI = MRI->getVRegDef(InReg); MachineInstr *DefMI = MRI->getVRegDef(InReg);
if (!DefMI || (DefMI->getOpcode() != RISCV::PseudoVSETVLI && if (!DefMI || !isVectorConfigInstr(*DefMI))
DefMI->getOpcode() != RISCV::PseudoVSETVLIX0 &&
DefMI->getOpcode() != RISCV::PseudoVSETIVLI))
return true; return true;
// We found a VSET(I)VLI make sure it matches the output of the // We found a VSET(I)VLI make sure it matches the output of the
@ -1008,9 +1008,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
for (MachineInstr &MI : MBB) { for (MachineInstr &MI : MBB) {
// If this is an explicit VSETVLI or VSETIVLI, update our state. // If this is an explicit VSETVLI or VSETIVLI, update our state.
if (MI.getOpcode() == RISCV::PseudoVSETVLI || if (isVectorConfigInstr(MI)) {
MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
MI.getOpcode() == RISCV::PseudoVSETIVLI) {
// Conservatively, mark the VL and VTYPE as live. // Conservatively, mark the VL and VTYPE as live.
assert(MI.getOperand(3).getReg() == RISCV::VL && assert(MI.getOperand(3).getReg() == RISCV::VL &&
MI.getOperand(4).getReg() == RISCV::VTYPE && MI.getOperand(4).getReg() == RISCV::VTYPE &&