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[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. 

The "dead" markings allow existing target-independent optimizations,
like MachineSink, to trigger more frequently. The CPSR defs would have
eventually been marked dead by LiveVariables, so this only affects
optimizations before regalloc.

The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible
with this change: the transform adds a use to an otherwise dead def
of CPSR. This is covered by existing regression tests.

thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the
generated code; I'll fix it in D53452.

Differential Revision: https://reviews.llvm.org/D53453

llvm-svn: 345420
This commit is contained in:
Eli Friedman 2018-10-26 19:32:24 +00:00
parent 6822bd79ac
commit 2ac1162917
11 changed files with 235 additions and 212 deletions
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2
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -959,7 +959,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
}
// Finally mark unused registers as dead.
if (!UsedRegs.empty() || II.getImplicitDefs())
if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
// Run post-isel target hook to adjust this instruction if needed.

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -2963,6 +2963,8 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
MI->clearRegisterDeads(ARM::CPSR);
return true;
}

3
llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
View File

@ -153,11 +153,10 @@ define i32 @test_tst_assessment(i32 %a, i32 %b) {
; THUMB-NEXT: movs r2, r0
; THUMB-NEXT: movs r0, #1
; THUMB-NEXT: ands r0, r2
; THUMB-NEXT: subs r2, r0, #1
; THUMB-NEXT: lsls r1, r1, #31
; THUMB-NEXT: beq .LBB2_2
; THUMB-NEXT: @ %bb.1:
; THUMB-NEXT: movs r0, r2
; THUMB-NEXT: subs r0, r0, #1
; THUMB-NEXT: .LBB2_2:
; THUMB-NEXT: bx lr
;

26
llvm/test/CodeGen/ARM/cmn.ll
View File

@ -15,16 +15,15 @@ define i32 @compare_i_gt(i32 %a) {
;
; T1-LABEL: compare_i_gt:
; T1: @ %bb.0: @ %entry
; T1-NEXT: mov r1, r0
; T1-NEXT: movs r0, #77
; T1-NEXT: mvns r3, r0
; T1-NEXT: movs r0, #42
; T1-NEXT: movs r2, #24
; T1-NEXT: cmp r1, r3
; T1-NEXT: movs r1, #77
; T1-NEXT: mvns r1, r1
; T1-NEXT: cmp r0, r1
; T1-NEXT: bgt .LBB0_2
; T1-NEXT: @ %bb.1: @ %entry
; T1-NEXT: mov r0, r2
; T1-NEXT: .LBB0_2: @ %entry
; T1-NEXT: movs r0, #24
; T1-NEXT: bx lr
; T1-NEXT: .LBB0_2:
; T1-NEXT: movs r0, #42
; T1-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, -78
@ -44,14 +43,13 @@ define i32 @compare_r_eq(i32 %a, i32 %b) {
;
; T1-LABEL: compare_r_eq:
; T1: @ %bb.0: @ %entry
; T1-NEXT: mov r2, r0
; T1-NEXT: movs r0, #42
; T1-NEXT: movs r3, #24
; T1-NEXT: cmn r2, r1
; T1-NEXT: cmn r0, r1
; T1-NEXT: beq .LBB1_2
; T1-NEXT: @ %bb.1: @ %entry
; T1-NEXT: mov r0, r3
; T1-NEXT: .LBB1_2: @ %entry
; T1-NEXT: movs r0, #24
; T1-NEXT: bx lr
; T1-NEXT: .LBB1_2:
; T1-NEXT: movs r0, #42
; T1-NEXT: bx lr
entry:
%sub = sub nsw i32 0, %b

19
llvm/test/CodeGen/ARM/intrinsics-overflow.ll
View File

@ -38,14 +38,9 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
; ARM: movvc r[[R0]], #0
; ARM: mov pc, lr
; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]]
; THUMBV6: adds r[[R3:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
; THUMBV6: movs r[[R0]], #0
; THUMBV6: movs r[[R1]], #1
; THUMBV6: cmp r[[R3]], r[[R2]]
; THUMBV6: bvc .L[[LABEL:.*]]
; THUMBV6: mov r[[R0]], r[[R1]]
; THUMBV6: .L[[LABEL]]:
; THUMBV6: adds r1, r0, r1
; THUMBV6: cmp r1, r0
; THUMBV6: bvc .LBB1_2
; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
; THUMBV7: mov.w r[[R0:[0-9]+]], #1
@ -94,12 +89,8 @@ define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
; ARM: cmp r[[R0]], r[[R1]]
; ARM: movvc r[[R2]], #0
; THUMBV6: movs r[[R0]], #0
; THUMBV6: movs r[[R3:[0-9]+]], #1
; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]]
; THUMBV6: bvc .L[[LABEL:.*]]
; THUMBV6: mov r[[R0]], r[[R3]]
; THUMBV6: .L[[LABEL]]:
; THUMBV6: cmp r0, r1
; THUMBV6: bvc .LBB3_2
; THUMBV7: movs r[[R2:[0-9]+]], #1
; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]]

10
llvm/test/CodeGen/ARM/select-imm.ll
View File

@ -24,12 +24,8 @@ entry:
; ARMT2: movwgt [[R]], #123
; THUMB1-LABEL: t1:
; THUMB1: mov r1, r0
; THUMB1: movs r2, #255
; THUMB1: adds r2, #102
; THUMB1: movs r0, #123
; THUMB1: cmp r1, #1
; THUMB1: bgt
; THUMB1: cmp r0, #1
; THUMB1: bgt .LBB0_2
; THUMB2-LABEL: t1:
; THUMB2: movw [[R:r[0-1]]], #357
@ -144,7 +140,7 @@ entry:
; THUMB1-LABEL: t6:
; THUMB1: cmp r{{[0-9]+}}, #0
; THUMB1: bne
; THUMB1: beq
; THUMB2-LABEL: t6:
; THUMB2-NOT: mov

15
llvm/test/CodeGen/Thumb/branchless-cmp.ll
View File

@ -85,14 +85,15 @@ entry:
%cond = select i1 %cmp, i32 0, i32 4
ret i32 %cond
; CHECK-LABEL: test4a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: mov r2, r0
; CHECK: bb.0:
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: bne .LBB6_2
; CHECK-NEXT: bb.1:
; CHECK-NEXT: movs r0, #4
; CHECK-NEXT: bx lr
; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: movs r3, #4
; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: bne .[[BRANCH:[A-Z0-9_]+]]
; CHECK: mov r0, r3
; CHECK: .[[BRANCH]]:
; CHECK-NEXT: bx lr
}
define i32 @test4b(i32 %a, i32 %b) {

1
llvm/test/CodeGen/Thumb/consthoist-few-dependents.ll
View File

@ -23,7 +23,6 @@ target triple = "thumbv6m-none-unknown-musleabi"
; LLC-LABEL: avalon
; LLC-DAG: movs r{{[0-9]+}}, #0
; LLC-DAG: movs r{{[0-9]+}}, #0
; LLC-DAG: movs r{{[0-9]+}}, #1
; LLC-NOT: add

4
llvm/test/CodeGen/Thumb/select.ll
View File

@ -73,10 +73,10 @@ define double @f7(double %a, double %b) {
ret double %tmp1
}
; CHECK-LABEL: f7:
; CHECK: blt
; CHECK: {{blt|bge}}
; CHECK: {{blt|bge}}
; CHECK: __ltdf2
; CHECK-EABI-LABEL: f7:
; CHECK-EABI: __aeabi_dcmplt
; CHECK-EABI: bne
; CHECK-EABI: {{bne|beq}}
; CHECK-EABI: {{bne|beq}}

356
llvm/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll
View File

@ -3,168 +3,200 @@
define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; THUMBV6-LABEL: muloti_test:
; THUMBV6: push {r4, r5, r6, r7, lr}
; THUMBV6: sub sp, #84
; THUMBV6-NEXT: mov r6, r3
; THUMBV6-NEXT: mov r7, r2
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: movs r5, #0
; THUMBV6-NEXT: mov r0, sp
; THUMBV6-NEXT: str r5, [r0, #12]
; THUMBV6-NEXT: str r5, [r0, #8]
; THUMBV6-NEXT: ldr r1, [sp, #116]
; THUMBV6-NEXT: str r1, [sp, #68] @ 4-byte Spill
; THUMBV6-NEXT: str r1, [r0, #4]
; THUMBV6-NEXT: ldr r1, [sp, #112]
; THUMBV6-NEXT: str r1, [sp, #32] @ 4-byte Spill
; THUMBV6-NEXT: str r1, [r0]
; THUMBV6-NEXT: mov r0, r2
; THUMBV6-NEXT: mov r1, r3
; THUMBV6-NEXT: mov r2, r5
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __multi3
; THUMBV6-NEXT: str r2, [sp, #40] @ 4-byte Spill
; THUMBV6-NEXT: str r3, [sp, #44] @ 4-byte Spill
; THUMBV6-NEXT: str r4, [sp, #72] @ 4-byte Spill
; THUMBV6-NEXT: stm r4!, {r0, r1}
; THUMBV6-NEXT: ldr r4, [sp, #120]
; THUMBV6-NEXT: str r6, [sp, #60] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r6
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r4
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: mov r6, r0
; THUMBV6-NEXT: str r1, [sp, #52] @ 4-byte Spill
; THUMBV6-NEXT: ldr r0, [sp, #124]
; THUMBV6-NEXT: str r0, [sp, #80] @ 4-byte Spill
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r7
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: str r1, [sp, #28] @ 4-byte Spill
; THUMBV6-NEXT: adds r6, r0, r6
; THUMBV6-NEXT: str r4, [sp, #64] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r4
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r7
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: str r0, [sp, #24] @ 4-byte Spill
; THUMBV6-NEXT: adds r0, r1, r6
; THUMBV6-NEXT: str r0, [sp, #20] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r5
; THUMBV6-NEXT: adcs r0, r5
; THUMBV6-NEXT: str r0, [sp, #48] @ 4-byte Spill
; THUMBV6-NEXT: ldr r7, [sp, #104]
; THUMBV6-NEXT: ldr r0, [sp, #68] @ 4-byte Reload
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r7
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: mov r6, r0
; THUMBV6-NEXT: str r1, [sp, #56] @ 4-byte Spill
; THUMBV6-NEXT: ldr r0, [sp, #108]
; THUMBV6-NEXT: str r0, [sp, #76] @ 4-byte Spill
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: ldr r4, [sp, #32] @ 4-byte Reload
; THUMBV6-NEXT: mov r2, r4
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: str r1, [sp, #36] @ 4-byte Spill
; THUMBV6-NEXT: adds r6, r0, r6
; THUMBV6-NEXT: mov r0, r7
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r4
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: adds r2, r1, r6
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: adcs r1, r5
; THUMBV6-NEXT: ldr r3, [sp, #24] @ 4-byte Reload
; THUMBV6-NEXT: adds r0, r0, r3
; THUMBV6-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
; THUMBV6-NEXT: adcs r2, r3
; THUMBV6-NEXT: ldr r3, [sp, #40] @ 4-byte Reload
; THUMBV6-NEXT: adds r0, r3, r0
; THUMBV6-NEXT: ldr r3, [sp, #72] @ 4-byte Reload
; THUMBV6-NEXT: str r0, [r3, #8]
; THUMBV6-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
; THUMBV6-NEXT: adcs r2, r0
; THUMBV6-NEXT: str r2, [r3, #12]
; THUMBV6-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; THUMBV6-NEXT: adcs r5, r5
; THUMBV6-NEXT: movs r0, #1
; THUMBV6-NEXT: cmp r2, #0
; THUMBV6-NEXT: mov r3, r0
; THUMBV6-NEXT: bne .LBB0_2
; THUMBV6: mov r3, r2
; THUMBV6: ldr r2, [sp, #60] @ 4-byte Reload
; THUMBV6-NEXT: cmp r2, #0
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: bne .LBB0_4
; THUMBV6: mov r4, r2
; THUMBV6: ldr r2, [sp, #80] @ 4-byte Reload
; THUMBV6-NEXT: cmp r2, #0
; THUMBV6-NEXT: mov r2, r0
; THUMBV6-NEXT: bne .LBB0_6
; THUMBV6: ldr r2, [sp, #80] @ 4-byte Reload
; THUMBV6: ands r2, r4
; THUMBV6-NEXT: orrs r2, r3
; THUMBV6-NEXT: ldr r4, [sp, #52] @ 4-byte Reload
; THUMBV6-NEXT: cmp r4, #0
; THUMBV6-NEXT: mov r3, r0
; THUMBV6-NEXT: bne .LBB0_8
; THUMBV6: mov r3, r4
; THUMBV6: orrs r2, r3
; THUMBV6-NEXT: ldr r3, [sp, #48] @ 4-byte Reload
; THUMBV6-NEXT: orrs r2, r3
; THUMBV6-NEXT: ldr r3, [sp, #36] @ 4-byte Reload
; THUMBV6-NEXT: cmp r3, #0
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: bne .LBB0_10
; THUMBV6: mov r4, r3
; THUMBV6: ldr r3, [sp, #68] @ 4-byte Reload
; THUMBV6-NEXT: cmp r3, #0
; THUMBV6-NEXT: mov r6, r0
; THUMBV6-NEXT: bne .LBB0_12
; THUMBV6: mov r6, r3
; THUMBV6: ldr r3, [sp, #76] @ 4-byte Reload
; THUMBV6-NEXT: cmp r3, #0
; THUMBV6-NEXT: mov r3, r0
; THUMBV6-NEXT: bne .LBB0_14
; THUMBV6: ldr r3, [sp, #76] @ 4-byte Reload
; THUMBV6: ands r3, r6
; THUMBV6-NEXT: orrs r3, r4
; THUMBV6-NEXT: ldr r6, [sp, #56] @ 4-byte Reload
; THUMBV6-NEXT: cmp r6, #0
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: bne .LBB0_16
; THUMBV6: mov r4, r6
; THUMBV6: orrs r3, r4
; THUMBV6-NEXT: orrs r3, r1
; THUMBV6-NEXT: ldr r4, [sp, #64] @ 4-byte Reload
; THUMBV6-NEXT: ldr r1, [sp, #80] @ 4-byte Reload
; THUMBV6-NEXT: orrs r4, r1
; THUMBV6-NEXT: cmp r4, #0
; THUMBV6-NEXT: mov r1, r0
; THUMBV6-NEXT: bne .LBB0_18
; THUMBV6: mov r1, r4
; THUMBV6: ldr r4, [sp, #76] @ 4-byte Reload
; THUMBV6-NEXT: orrs r7, r4
; THUMBV6-NEXT: cmp r7, #0
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: bne .LBB0_20
; THUMBV6: mov r4, r7
; THUMBV6: ands r4, r1
; THUMBV6-NEXT: orrs r4, r3
; THUMBV6-NEXT: orrs r4, r2
; THUMBV6-NEXT: orrs r4, r5
; THUMBV6-NEXT: ands r4, r0
; THUMBV6-NEXT: ldr r0, [sp, #72] @ 4-byte Reload
; THUMBV6-NEXT: strb r4, [r0, #16]
; THUMBV6-NEXT: add sp, #84
; THUMBV6-NEXT: pop {r4, r5, r6, r7, pc}
; THUMBV6: @ %bb.0: @ %start
; THUMBV6-NEXT: .save {r4, r5, r6, r7, lr}
; THUMBV6-NEXT: push {r4, r5, r6, r7, lr}
; THUMBV6-NEXT: .pad #84
; THUMBV6-NEXT: sub sp, #84
; THUMBV6-NEXT: mov r6, r3
; THUMBV6-NEXT: mov r7, r2
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: movs r5, #0
; THUMBV6-NEXT: mov r0, sp
; THUMBV6-NEXT: str r5, [r0, #12]
; THUMBV6-NEXT: str r5, [r0, #8]
; THUMBV6-NEXT: ldr r1, [sp, #116]
; THUMBV6-NEXT: str r1, [sp, #72] @ 4-byte Spill
; THUMBV6-NEXT: str r1, [r0, #4]
; THUMBV6-NEXT: ldr r1, [sp, #112]
; THUMBV6-NEXT: str r1, [sp, #44] @ 4-byte Spill
; THUMBV6-NEXT: str r1, [r0]
; THUMBV6-NEXT: mov r0, r2
; THUMBV6-NEXT: mov r1, r3
; THUMBV6-NEXT: mov r2, r5
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __multi3
; THUMBV6-NEXT: str r2, [sp, #36] @ 4-byte Spill
; THUMBV6-NEXT: str r3, [sp, #40] @ 4-byte Spill
; THUMBV6-NEXT: str r4, [sp, #76] @ 4-byte Spill
; THUMBV6-NEXT: stm r4!, {r0, r1}
; THUMBV6-NEXT: ldr r4, [sp, #120]
; THUMBV6-NEXT: str r6, [sp, #56] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r6
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r4
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: mov r6, r0
; THUMBV6-NEXT: str r1, [sp, #48] @ 4-byte Spill
; THUMBV6-NEXT: ldr r0, [sp, #124]
; THUMBV6-NEXT: str r0, [sp, #80] @ 4-byte Spill
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r7
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: str r1, [sp, #28] @ 4-byte Spill
; THUMBV6-NEXT: adds r6, r0, r6
; THUMBV6-NEXT: str r4, [sp, #68] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r4
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r7
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: str r0, [sp, #20] @ 4-byte Spill
; THUMBV6-NEXT: adds r0, r1, r6
; THUMBV6-NEXT: str r0, [sp, #16] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r5
; THUMBV6-NEXT: adcs r0, r5
; THUMBV6-NEXT: str r0, [sp, #64] @ 4-byte Spill
; THUMBV6-NEXT: ldr r7, [sp, #104]
; THUMBV6-NEXT: ldr r0, [sp, #72] @ 4-byte Reload
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r7
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: mov r6, r0
; THUMBV6-NEXT: str r1, [sp, #52] @ 4-byte Spill
; THUMBV6-NEXT: ldr r0, [sp, #108]
; THUMBV6-NEXT: str r0, [sp, #60] @ 4-byte Spill
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: ldr r4, [sp, #44] @ 4-byte Reload
; THUMBV6-NEXT: mov r2, r4
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: str r1, [sp, #32] @ 4-byte Spill
; THUMBV6-NEXT: adds r6, r0, r6
; THUMBV6-NEXT: str r7, [sp, #24] @ 4-byte Spill
; THUMBV6-NEXT: mov r0, r7
; THUMBV6-NEXT: mov r1, r5
; THUMBV6-NEXT: mov r2, r4
; THUMBV6-NEXT: mov r3, r5
; THUMBV6-NEXT: bl __aeabi_lmul
; THUMBV6-NEXT: adds r1, r1, r6
; THUMBV6-NEXT: mov r2, r5
; THUMBV6-NEXT: adcs r2, r5
; THUMBV6-NEXT: str r2, [sp, #44] @ 4-byte Spill
; THUMBV6-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
; THUMBV6-NEXT: adds r0, r0, r2
; THUMBV6-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; THUMBV6-NEXT: adcs r1, r2
; THUMBV6-NEXT: ldr r2, [sp, #36] @ 4-byte Reload
; THUMBV6-NEXT: adds r0, r2, r0
; THUMBV6-NEXT: ldr r2, [sp, #76] @ 4-byte Reload
; THUMBV6-NEXT: str r0, [r2, #8]
; THUMBV6-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
; THUMBV6-NEXT: adcs r1, r0
; THUMBV6-NEXT: str r1, [r2, #12]
; THUMBV6-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
; THUMBV6-NEXT: adcs r5, r5
; THUMBV6-NEXT: movs r0, #1
; THUMBV6-NEXT: cmp r1, #0
; THUMBV6-NEXT: mov r2, r0
; THUMBV6-NEXT: bne .LBB0_2
; THUMBV6-NEXT: @ %bb.1: @ %start
; THUMBV6-NEXT: mov r2, r1
; THUMBV6-NEXT: .LBB0_2: @ %start
; THUMBV6-NEXT: str r2, [sp, #40] @ 4-byte Spill
; THUMBV6-NEXT: ldr r1, [sp, #56] @ 4-byte Reload
; THUMBV6-NEXT: cmp r1, #0
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: bne .LBB0_4
; THUMBV6-NEXT: @ %bb.3: @ %start
; THUMBV6-NEXT: mov r4, r1
; THUMBV6-NEXT: .LBB0_4: @ %start
; THUMBV6-NEXT: ldr r1, [sp, #80] @ 4-byte Reload
; THUMBV6-NEXT: cmp r1, #0
; THUMBV6-NEXT: mov r2, r0
; THUMBV6-NEXT: ldr r3, [sp, #48] @ 4-byte Reload
; THUMBV6-NEXT: ldr r6, [sp, #32] @ 4-byte Reload
; THUMBV6-NEXT: bne .LBB0_6
; THUMBV6-NEXT: @ %bb.5: @ %start
; THUMBV6-NEXT: ldr r2, [sp, #80] @ 4-byte Reload
; THUMBV6-NEXT: .LBB0_6: @ %start
; THUMBV6-NEXT: cmp r3, #0
; THUMBV6-NEXT: mov r7, r0
; THUMBV6-NEXT: ldr r1, [sp, #72] @ 4-byte Reload
; THUMBV6-NEXT: bne .LBB0_8
; THUMBV6-NEXT: @ %bb.7: @ %start
; THUMBV6-NEXT: mov r7, r3
; THUMBV6-NEXT: .LBB0_8: @ %start
; THUMBV6-NEXT: cmp r6, #0
; THUMBV6-NEXT: mov r3, r0
; THUMBV6-NEXT: bne .LBB0_10
; THUMBV6-NEXT: @ %bb.9: @ %start
; THUMBV6-NEXT: mov r3, r6
; THUMBV6-NEXT: .LBB0_10: @ %start
; THUMBV6-NEXT: cmp r1, #0
; THUMBV6-NEXT: mov r6, r1
; THUMBV6-NEXT: mov r1, r0
; THUMBV6-NEXT: bne .LBB0_12
; THUMBV6-NEXT: @ %bb.11: @ %start
; THUMBV6-NEXT: mov r1, r6
; THUMBV6-NEXT: .LBB0_12: @ %start
; THUMBV6-NEXT: str r7, [sp, #72] @ 4-byte Spill
; THUMBV6-NEXT: ands r2, r4
; THUMBV6-NEXT: ldr r6, [sp, #60] @ 4-byte Reload
; THUMBV6-NEXT: cmp r6, #0
; THUMBV6-NEXT: mov r4, r0
; THUMBV6-NEXT: bne .LBB0_14
; THUMBV6-NEXT: @ %bb.13: @ %start
; THUMBV6-NEXT: mov r4, r6
; THUMBV6-NEXT: .LBB0_14: @ %start
; THUMBV6-NEXT: ldr r7, [sp, #40] @ 4-byte Reload
; THUMBV6-NEXT: orrs r2, r7
; THUMBV6-NEXT: ands r4, r1
; THUMBV6-NEXT: orrs r4, r3
; THUMBV6-NEXT: ldr r3, [sp, #52] @ 4-byte Reload
; THUMBV6-NEXT: cmp r3, #0
; THUMBV6-NEXT: mov r1, r0
; THUMBV6-NEXT: bne .LBB0_16
; THUMBV6-NEXT: @ %bb.15: @ %start
; THUMBV6-NEXT: mov r1, r3
; THUMBV6-NEXT: .LBB0_16: @ %start
; THUMBV6-NEXT: ldr r3, [sp, #72] @ 4-byte Reload
; THUMBV6-NEXT: orrs r2, r3
; THUMBV6-NEXT: orrs r4, r1
; THUMBV6-NEXT: ldr r1, [sp, #68] @ 4-byte Reload
; THUMBV6-NEXT: ldr r3, [sp, #80] @ 4-byte Reload
; THUMBV6-NEXT: orrs r1, r3
; THUMBV6-NEXT: cmp r1, #0
; THUMBV6-NEXT: mov r3, r0
; THUMBV6-NEXT: bne .LBB0_18
; THUMBV6-NEXT: @ %bb.17: @ %start
; THUMBV6-NEXT: mov r3, r1
; THUMBV6-NEXT: .LBB0_18: @ %start
; THUMBV6-NEXT: ldr r1, [sp, #64] @ 4-byte Reload
; THUMBV6-NEXT: orrs r2, r1
; THUMBV6-NEXT: ldr r1, [sp, #44] @ 4-byte Reload
; THUMBV6-NEXT: orrs r4, r1
; THUMBV6-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; THUMBV6-NEXT: orrs r1, r6
; THUMBV6-NEXT: mov r6, r1
; THUMBV6-NEXT: cmp r1, #0
; THUMBV6-NEXT: mov r1, r0
; THUMBV6-NEXT: bne .LBB0_20
; THUMBV6-NEXT: @ %bb.19: @ %start
; THUMBV6-NEXT: mov r1, r6
; THUMBV6-NEXT: .LBB0_20: @ %start
; THUMBV6-NEXT: ands r1, r3
; THUMBV6-NEXT: orrs r1, r4
; THUMBV6-NEXT: orrs r1, r2
; THUMBV6-NEXT: orrs r1, r5
; THUMBV6-NEXT: ands r1, r0
; THUMBV6-NEXT: ldr r0, [sp, #76] @ 4-byte Reload
; THUMBV6-NEXT: strb r1, [r0, #16]
; THUMBV6-NEXT: add sp, #84
; THUMBV6-NEXT: pop {r4, r5, r6, r7, pc}
start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
%1 = extractvalue { i128, i1 } %0, 0

9
llvm/test/CodeGen/Thumb2/thumb2-tbh.ll
View File

@ -1,6 +1,11 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T2
; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T1
; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=CHECK --check-prefix=T1
; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=T1DISABLED
; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T1
; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=CHECK --check-prefix=T1
; FIXME: Thumb1 tests temporarily disabled; MachineLICM is now hoisting the
; subs, so the jump table can't be formed.
; T1DISABLED: .data_region jt32
; Thumb2 target should reorder the bb's in order to use tbb / tbh.