forked from OSchip/llvm-project
[x86] add tests for potential memcmp expansion (PR33325); NFC
llvm-svn: 321542
This commit is contained in:
Sanjay Patel
parent
a19d42f972
commit
2aae217a97
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@ -138,3 +138,255 @@ define i32 @eq_i256(<4 x i64> %x, <4 x i64> %y) {
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ret i32 %zext
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}
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; This test models the expansion of 'memcmp(a, b, 32) != 0'
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; if we allowed 2 pairs of 16-byte loads per block.
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define i32 @ne_i128_pair(i128* %a, i128* %b) {
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; SSE2-LABEL: ne_i128_pair:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movq (%rdi), %rax
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; SSE2-NEXT: movq 8(%rdi), %rcx
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; SSE2-NEXT: xorq (%rsi), %rax
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; SSE2-NEXT: xorq 8(%rsi), %rcx
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; SSE2-NEXT: movq 24(%rdi), %rdx
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; SSE2-NEXT: movq 16(%rdi), %rdi
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; SSE2-NEXT: xorq 16(%rsi), %rdi
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; SSE2-NEXT: orq %rax, %rdi
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; SSE2-NEXT: xorq 24(%rsi), %rdx
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; SSE2-NEXT: orq %rcx, %rdx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: orq %rdi, %rdx
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; SSE2-NEXT: setne %al
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; SSE2-NEXT: retq
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;
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; AVX2-LABEL: ne_i128_pair:
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; AVX2: # %bb.0:
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; AVX2-NEXT: movq (%rdi), %rax
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; AVX2-NEXT: movq 8(%rdi), %rcx
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; AVX2-NEXT: xorq (%rsi), %rax
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; AVX2-NEXT: xorq 8(%rsi), %rcx
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; AVX2-NEXT: movq 24(%rdi), %rdx
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; AVX2-NEXT: movq 16(%rdi), %rdi
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; AVX2-NEXT: xorq 16(%rsi), %rdi
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; AVX2-NEXT: orq %rax, %rdi
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; AVX2-NEXT: xorq 24(%rsi), %rdx
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; AVX2-NEXT: orq %rcx, %rdx
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; AVX2-NEXT: xorl %eax, %eax
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; AVX2-NEXT: orq %rdi, %rdx
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; AVX2-NEXT: setne %al
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; AVX2-NEXT: retq
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%a0 = load i128, i128* %a
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%b0 = load i128, i128* %b
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%xor1 = xor i128 %a0, %b0
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%ap1 = getelementptr i128, i128* %a, i128 1
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%bp1 = getelementptr i128, i128* %b, i128 1
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%a1 = load i128, i128* %ap1
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%b1 = load i128, i128* %bp1
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%xor2 = xor i128 %a1, %b1
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%or = or i128 %xor1, %xor2
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%cmp = icmp ne i128 %or, 0
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%z = zext i1 %cmp to i32
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ret i32 %z
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}
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; This test models the expansion of 'memcmp(a, b, 32) == 0'
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; if we allowed 2 pairs of 16-byte loads per block.
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define i32 @eq_i128_pair(i128* %a, i128* %b) {
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; SSE2-LABEL: eq_i128_pair:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movq (%rdi), %rax
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; SSE2-NEXT: movq 8(%rdi), %rcx
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; SSE2-NEXT: xorq (%rsi), %rax
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; SSE2-NEXT: xorq 8(%rsi), %rcx
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; SSE2-NEXT: movq 24(%rdi), %rdx
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; SSE2-NEXT: movq 16(%rdi), %rdi
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; SSE2-NEXT: xorq 16(%rsi), %rdi
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; SSE2-NEXT: orq %rax, %rdi
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; SSE2-NEXT: xorq 24(%rsi), %rdx
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; SSE2-NEXT: orq %rcx, %rdx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: orq %rdi, %rdx
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; AVX2-LABEL: eq_i128_pair:
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; AVX2: # %bb.0:
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; AVX2-NEXT: movq (%rdi), %rax
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; AVX2-NEXT: movq 8(%rdi), %rcx
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; AVX2-NEXT: xorq (%rsi), %rax
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; AVX2-NEXT: xorq 8(%rsi), %rcx
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; AVX2-NEXT: movq 24(%rdi), %rdx
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; AVX2-NEXT: movq 16(%rdi), %rdi
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; AVX2-NEXT: xorq 16(%rsi), %rdi
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; AVX2-NEXT: orq %rax, %rdi
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; AVX2-NEXT: xorq 24(%rsi), %rdx
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; AVX2-NEXT: orq %rcx, %rdx
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; AVX2-NEXT: xorl %eax, %eax
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; AVX2-NEXT: orq %rdi, %rdx
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; AVX2-NEXT: sete %al
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; AVX2-NEXT: retq
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%a0 = load i128, i128* %a
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%b0 = load i128, i128* %b
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%xor1 = xor i128 %a0, %b0
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%ap1 = getelementptr i128, i128* %a, i128 1
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%bp1 = getelementptr i128, i128* %b, i128 1
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%a1 = load i128, i128* %ap1
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%b1 = load i128, i128* %bp1
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%xor2 = xor i128 %a1, %b1
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%or = or i128 %xor1, %xor2
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%cmp = icmp eq i128 %or, 0
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%z = zext i1 %cmp to i32
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ret i32 %z
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}
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; This test models the expansion of 'memcmp(a, b, 64) != 0'
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; if we allowed 2 pairs of 32-byte loads per block.
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define i32 @ne_i256_pair(i256* %a, i256* %b) {
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; SSE2-LABEL: ne_i256_pair:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movq 16(%rdi), %r9
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; SSE2-NEXT: movq 24(%rdi), %r11
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; SSE2-NEXT: movq (%rdi), %r8
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; SSE2-NEXT: movq 8(%rdi), %r10
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; SSE2-NEXT: xorq 8(%rsi), %r10
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; SSE2-NEXT: xorq 24(%rsi), %r11
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; SSE2-NEXT: xorq (%rsi), %r8
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; SSE2-NEXT: xorq 16(%rsi), %r9
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; SSE2-NEXT: movq 48(%rdi), %rdx
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; SSE2-NEXT: movq 32(%rdi), %rax
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; SSE2-NEXT: movq 56(%rdi), %rcx
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; SSE2-NEXT: movq 40(%rdi), %rdi
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; SSE2-NEXT: xorq 40(%rsi), %rdi
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; SSE2-NEXT: xorq 56(%rsi), %rcx
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; SSE2-NEXT: orq %r11, %rcx
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; SSE2-NEXT: orq %rdi, %rcx
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; SSE2-NEXT: orq %r10, %rcx
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; SSE2-NEXT: xorq 32(%rsi), %rax
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; SSE2-NEXT: xorq 48(%rsi), %rdx
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; SSE2-NEXT: orq %r9, %rdx
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; SSE2-NEXT: orq %rax, %rdx
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; SSE2-NEXT: orq %r8, %rdx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: orq %rcx, %rdx
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; SSE2-NEXT: setne %al
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; SSE2-NEXT: retq
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;
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; AVX2-LABEL: ne_i256_pair:
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; AVX2: # %bb.0:
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; AVX2-NEXT: movq 16(%rdi), %r9
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; AVX2-NEXT: movq 24(%rdi), %r11
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; AVX2-NEXT: movq (%rdi), %r8
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; AVX2-NEXT: movq 8(%rdi), %r10
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; AVX2-NEXT: xorq 8(%rsi), %r10
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; AVX2-NEXT: xorq 24(%rsi), %r11
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; AVX2-NEXT: xorq (%rsi), %r8
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; AVX2-NEXT: xorq 16(%rsi), %r9
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; AVX2-NEXT: movq 48(%rdi), %rdx
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; AVX2-NEXT: movq 32(%rdi), %rax
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; AVX2-NEXT: movq 56(%rdi), %rcx
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; AVX2-NEXT: movq 40(%rdi), %rdi
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; AVX2-NEXT: xorq 40(%rsi), %rdi
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; AVX2-NEXT: xorq 56(%rsi), %rcx
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; AVX2-NEXT: orq %r11, %rcx
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; AVX2-NEXT: orq %rdi, %rcx
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; AVX2-NEXT: orq %r10, %rcx
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; AVX2-NEXT: xorq 32(%rsi), %rax
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; AVX2-NEXT: xorq 48(%rsi), %rdx
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; AVX2-NEXT: orq %r9, %rdx
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; AVX2-NEXT: orq %rax, %rdx
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; AVX2-NEXT: orq %r8, %rdx
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; AVX2-NEXT: xorl %eax, %eax
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; AVX2-NEXT: orq %rcx, %rdx
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; AVX2-NEXT: setne %al
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; AVX2-NEXT: retq
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%a0 = load i256, i256* %a
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%b0 = load i256, i256* %b
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%xor1 = xor i256 %a0, %b0
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%ap1 = getelementptr i256, i256* %a, i256 1
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%bp1 = getelementptr i256, i256* %b, i256 1
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%a1 = load i256, i256* %ap1
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%b1 = load i256, i256* %bp1
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%xor2 = xor i256 %a1, %b1
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%or = or i256 %xor1, %xor2
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%cmp = icmp ne i256 %or, 0
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%z = zext i1 %cmp to i32
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ret i32 %z
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}
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; This test models the expansion of 'memcmp(a, b, 64) == 0'
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; if we allowed 2 pairs of 32-byte loads per block.
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define i32 @eq_i256_pair(i256* %a, i256* %b) {
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; SSE2-LABEL: eq_i256_pair:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movq 16(%rdi), %r9
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; SSE2-NEXT: movq 24(%rdi), %r11
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; SSE2-NEXT: movq (%rdi), %r8
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; SSE2-NEXT: movq 8(%rdi), %r10
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; SSE2-NEXT: xorq 8(%rsi), %r10
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; SSE2-NEXT: xorq 24(%rsi), %r11
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; SSE2-NEXT: xorq (%rsi), %r8
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; SSE2-NEXT: xorq 16(%rsi), %r9
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; SSE2-NEXT: movq 48(%rdi), %rdx
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; SSE2-NEXT: movq 32(%rdi), %rax
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; SSE2-NEXT: movq 56(%rdi), %rcx
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; SSE2-NEXT: movq 40(%rdi), %rdi
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; SSE2-NEXT: xorq 40(%rsi), %rdi
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; SSE2-NEXT: xorq 56(%rsi), %rcx
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; SSE2-NEXT: orq %r11, %rcx
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; SSE2-NEXT: orq %rdi, %rcx
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; SSE2-NEXT: orq %r10, %rcx
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; SSE2-NEXT: xorq 32(%rsi), %rax
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; SSE2-NEXT: xorq 48(%rsi), %rdx
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; SSE2-NEXT: orq %r9, %rdx
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; SSE2-NEXT: orq %rax, %rdx
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; SSE2-NEXT: orq %r8, %rdx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: orq %rcx, %rdx
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; AVX2-LABEL: eq_i256_pair:
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; AVX2: # %bb.0:
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; AVX2-NEXT: movq 16(%rdi), %r9
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; AVX2-NEXT: movq 24(%rdi), %r11
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; AVX2-NEXT: movq (%rdi), %r8
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; AVX2-NEXT: movq 8(%rdi), %r10
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; AVX2-NEXT: xorq 8(%rsi), %r10
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; AVX2-NEXT: xorq 24(%rsi), %r11
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; AVX2-NEXT: xorq (%rsi), %r8
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; AVX2-NEXT: xorq 16(%rsi), %r9
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; AVX2-NEXT: movq 48(%rdi), %rdx
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; AVX2-NEXT: movq 32(%rdi), %rax
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; AVX2-NEXT: movq 56(%rdi), %rcx
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; AVX2-NEXT: movq 40(%rdi), %rdi
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; AVX2-NEXT: xorq 40(%rsi), %rdi
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; AVX2-NEXT: xorq 56(%rsi), %rcx
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; AVX2-NEXT: orq %r11, %rcx
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; AVX2-NEXT: orq %rdi, %rcx
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; AVX2-NEXT: orq %r10, %rcx
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; AVX2-NEXT: xorq 32(%rsi), %rax
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; AVX2-NEXT: xorq 48(%rsi), %rdx
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; AVX2-NEXT: orq %r9, %rdx
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; AVX2-NEXT: orq %rax, %rdx
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; AVX2-NEXT: orq %r8, %rdx
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; AVX2-NEXT: xorl %eax, %eax
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; AVX2-NEXT: orq %rcx, %rdx
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; AVX2-NEXT: sete %al
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; AVX2-NEXT: retq
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%a0 = load i256, i256* %a
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%b0 = load i256, i256* %b
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%xor1 = xor i256 %a0, %b0
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%ap1 = getelementptr i256, i256* %a, i256 1
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%bp1 = getelementptr i256, i256* %b, i256 1
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%a1 = load i256, i256* %ap1
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%b1 = load i256, i256* %bp1
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%xor2 = xor i256 %a1, %b1
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%or = or i256 %xor1, %xor2
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%cmp = icmp eq i256 %or, 0
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%z = zext i1 %cmp to i32
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ret i32 %z
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}
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