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Moved the MachOWriter and ELFWriter out of the Target/* files. Placed the 

definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).

llvm-svn: 34034
This commit is contained in:
Bill Wendling 2007-02-08 01:39:44 +00:00
parent 59889ae93f
commit 2aa9a42f24
7 changed files with 20 additions and 36 deletions
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2
llvm/lib/Target/PowerPC/PPC.h
View File

@ -33,8 +33,6 @@ FunctionPass *createPPCAsmPrinterPass(std::ostream &OS,
PPCTargetMachine &TM);
FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
MachineCodeEmitter &MCE);
void addPPCMachOObjectWriterPass(FunctionPassManager &FPM, std::ostream &o,
PPCTargetMachine &tm);
} // end namespace llvm;
// Defines symbolic names for PowerPC registers. This defines a mapping from

6
llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
View File

@ -2,8 +2,9 @@
//
// The LLVM Compiler Infrastructure
//
// This file was developed by Bill Wendling and is distributed under the
// University of Illinois Open Source License. See LICENSE.TXT for details.
// This file was developed by Nate Begeman and Bill Wendling and is distributed
// under the University of Illinois Open Source License. See LICENSE.TXT for
// details.
//
//===----------------------------------------------------------------------===//
//
@ -25,7 +26,6 @@ PPCMachOWriterInfo::PPCMachOWriterInfo(const PPCTargetMachine &TM)
HDR_CPU_SUBTYPE_POWERPC_ALL) {}
PPCMachOWriterInfo::~PPCMachOWriterInfo() {}
/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
/// more PowerPC MachORelocation(s), add the new relocations to the
/// MachOSection, and rewrite the instruction at the section offset if required

16
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -129,16 +129,6 @@ bool PPCTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
return false;
}
bool PPCTargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast,
std::ostream &Out) {
// FIXME: until the macho writer is 100% functional, diable this by default.
return true;
// FIXME: support PPC ELF files at some point
addPPCMachOObjectWriterPass(PM, Out, *this);
return false;
}
bool PPCTargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
@ -161,3 +151,9 @@ bool PPCTargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
return false;
}
bool PPCTargetMachine::addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCCodeEmitterPass(*this, MCE));
return false;
}

4
llvm/lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -69,10 +69,10 @@ public:
virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);
virtual bool addObjectWriter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);
virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE);
};
/// PPC32TargetMachine - PowerPC 32-bit target machine.

6
llvm/lib/Target/X86/X86.h
View File

@ -46,12 +46,6 @@ FunctionPass *createX86CodePrinterPass(std::ostream &o, X86TargetMachine &tm);
FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM,
MachineCodeEmitter &MCE);
/// addX86ELFObjectWriterPass - Add passes to the FPM that output the generated
/// code as an ELF object file.
///
void addX86ELFObjectWriterPass(FunctionPassManager &FPM,
std::ostream &o, X86TargetMachine &tm);
/// createX86EmitCodeToMemory - Returns a pass that converts a register
/// allocated function into raw machine code in a dynamically
/// allocated chunk of memory.

15
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -163,15 +163,6 @@ bool X86TargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
return false;
}
bool X86TargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast,
std::ostream &Out) {
if (Subtarget.isTargetELF()) {
addX86ELFObjectWriterPass(PM, Out, *this);
return false;
}
return true;
}
bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
@ -185,3 +176,9 @@ bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
PM.add(createX86CodeEmitterPass(*this, MCE));
return false;
}
bool X86TargetMachine::addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
PM.add(createX86CodeEmitterPass(*this, MCE));
return false;
}

7
llvm/lib/Target/X86/X86TargetMachine.h
View File

@ -53,22 +53,21 @@ public:
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86ELFWriterInfo *getELFWriterInfo() const {
return &ELFWriterInfo;
return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
}
static unsigned getModuleMatchQuality(const Module &M);
static unsigned getJITMatchQuality();
// Set up the pass pipeline.
virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);
virtual bool addObjectWriter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);
virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE);
};
/// X86_32TargetMachine - X86 32-bit target machine.