forked from OSchip/llvm-project
AMDGPU: Remove Feature64BitPtr
This is a leftover from AMDIL that doesn't do anything and doesn't belong here. llvm-svn: 258606
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@ -73,11 +73,6 @@ def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
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"true",
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"true",
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"Enable single precision denormal handling">;
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"Enable single precision denormal handling">;
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def Feature64BitPtr : SubtargetFeature<"64BitPtr",
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"Is64bit",
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"true",
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"Specify if 64-bit addressing should be used">;
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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"R600ALUInst",
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"R600ALUInst",
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"false",
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"false",
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@ -247,17 +242,17 @@ def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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>;
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>;
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
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[FeatureFP64, FeatureLocalMemorySize32768,
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FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
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FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
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FeatureLDSBankCount32]>;
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FeatureLDSBankCount32]>;
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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[FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
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FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
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FeatureGCN1Encoding, FeatureCIInsts]>;
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FeatureGCN1Encoding, FeatureCIInsts]>;
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def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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[FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
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FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
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@ -66,7 +66,7 @@ AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
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AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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TargetMachine &TM)
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TargetMachine &TM)
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: AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
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: AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU),
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DumpCode(false), R600ALUInst(false), HasVertexCache(false),
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DumpCode(false), R600ALUInst(false), HasVertexCache(false),
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TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
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FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
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@ -59,7 +59,6 @@ public:
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private:
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private:
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std::string DevName;
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std::string DevName;
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bool Is64bit;
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bool DumpCode;
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bool DumpCode;
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bool R600ALUInst;
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bool R600ALUInst;
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bool HasVertexCache;
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bool HasVertexCache;
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@ -124,10 +123,6 @@ public:
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool is64bit() const {
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return Is64bit;
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}
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bool hasVertexCache() const {
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bool hasVertexCache() const {
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return HasVertexCache;
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return HasVertexCache;
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}
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}
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