forked from OSchip/llvm-project
[InstCombine] add tests from D32285 to show current problems; NFC
llvm-svn: 302475
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@ -1432,3 +1432,41 @@ define <2 x i32> @test90() {
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%tmp6 = bitcast <4 x half> <half undef, half undef, half undef, half 0xH3C00> to <2 x i32>
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%tmp6 = bitcast <4 x half> <half undef, half undef, half undef, half 0xH3C00> to <2 x i32>
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ret <2 x i32> %tmp6
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ret <2 x i32> %tmp6
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}
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}
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; Do not optimize to ashr i64 (shift by 48 > 96 - 64)
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define i64 @test91(i64 %A) {
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; CHECK-LABEL: @test91(
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; CHECK-NEXT: [[C:%.*]] = ashr i64 %A, 48
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; CHECK-NEXT: ret i64 [[C]]
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;
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%B = sext i64 %A to i96
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%C = lshr i96 %B, 48
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%D = trunc i96 %C to i64
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ret i64 %D
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}
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; Do optimize to ashr i64 (shift by 32 <= 96 - 64)
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define i64 @test92(i64 %A) {
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; CHECK-LABEL: @test92(
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; CHECK-NEXT: [[C:%.*]] = ashr i64 %A, 32
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; CHECK-NEXT: ret i64 [[C]]
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;
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%B = sext i64 %A to i96
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%C = lshr i96 %B, 32
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%D = trunc i96 %C to i64
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ret i64 %D
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}
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; When optimizing to ashr i32, don't shift by more than 31.
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define i32 @test93(i32 %A) {
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; CHECK-LABEL: @test93(
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; CHECK-NEXT: [[B:%.*]] = sext i32 %A to i96
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; CHECK-NEXT: [[C:%.*]] = lshr i96 [[B]], 64
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; CHECK-NEXT: [[D:%.*]] = trunc i96 [[C]] to i32
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; CHECK-NEXT: ret i32 [[D]]
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;
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%B = sext i32 %A to i96
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%C = lshr i96 %B, 64
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%D = trunc i96 %C to i32
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ret i32 %D
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}
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